Article: AMD's Mobile Strategy
By: Brett (ggtgp.delete@this.yahoo.com), December 26, 2011 6:56 pm
Room: Moderated Discussions
John Yates (john@yates-sheets.org) on 12/26/11 wrote:
---------------------------
>It is possible to find a middle ground between radically variable length instruction schemes and rigid single size.
>
>In the mid-80s I designed the instruction set for Apollo Computer's DN10K, a response
>to SUN's introduction of the SPARC architecture. I had previously used the:
>- PDP-8: all instructions were 12 bits
>- PDP-11: instruction were 16, 32 or 48 bits
>- VAX: made the x86 encoding look simple
>
>In time I came to see fixed size instructions as really a means to an end. The
>end is minimal pipeline stages ahead of issue, simple decode and simple issue.
>To that list Apollo added parallel issue. The design we ended up building[2] had
>2 instruction sizes: 32 bits and 64 bits. 64 bit instructions were required to
>be naturally aligned in the instruction stream. The instruction length was specified by a single bit.
>
>Though not really VLIW the DN10K could have been termed a "Moderately Wide Instruction
>Word" machine. Every cycle it could issue:
>- one integer, branch or memory reference instruction
>- optionally, one floating point instruction
>
>The floating point instruction set include a small number of 5-operand instructions
>in both single and double precision. These supported a 3-operand multiply combined
>with either a 2-operand accumulating add or sub or a convert float to integer.
>When combined with a large floating point register file these instructions made
>the machine particularly good at running linear algebra and graphics kernels.
>
>[1] http://www.linkedin.com/profile/view?id=308063&authType=name&authToken=03Xp&goback=%2Econ
>[2] http://www.google.com/patents?id=mgkXAAAAEBAJ&pg=PA11&dq=patent+5051885&hl=en&sa=X&ei=Zar4TuaNB8KksQLOkNXXAQ&ved=0CDMQ6AEwAA
>>
We liked our Apollo Computer DN10K's, too bad about the BiN designed FPU, is this what doomed it? Did they ever fix the bug with the FPU losing accuracy during task switching?
The climate change researcher at our university hated that every run of his model gave a different result on the DN10k. Garbage in garbage out I say.
The same code compiled for Cray also gave results he did not like. ;)
I would like a copy of the instruction set, is it available?
---------------------------
>It is possible to find a middle ground between radically variable length instruction schemes and rigid single size.
>
>In the mid-80s I designed the instruction set for Apollo Computer's DN10K, a response
>to SUN's introduction of the SPARC architecture. I had previously used the:
>- PDP-8: all instructions were 12 bits
>- PDP-11: instruction were 16, 32 or 48 bits
>- VAX: made the x86 encoding look simple
>
>In time I came to see fixed size instructions as really a means to an end. The
>end is minimal pipeline stages ahead of issue, simple decode and simple issue.
>To that list Apollo added parallel issue. The design we ended up building[2] had
>2 instruction sizes: 32 bits and 64 bits. 64 bit instructions were required to
>be naturally aligned in the instruction stream. The instruction length was specified by a single bit.
>
>Though not really VLIW the DN10K could have been termed a "Moderately Wide Instruction
>Word" machine. Every cycle it could issue:
>- one integer, branch or memory reference instruction
>- optionally, one floating point instruction
>
>The floating point instruction set include a small number of 5-operand instructions
>in both single and double precision. These supported a 3-operand multiply combined
>with either a 2-operand accumulating add or sub or a convert float to integer.
>When combined with a large floating point register file these instructions made
>the machine particularly good at running linear algebra and graphics kernels.
>
>[1] http://www.linkedin.com/profile/view?id=308063&authType=name&authToken=03Xp&goback=%2Econ
>[2] http://www.google.com/patents?id=mgkXAAAAEBAJ&pg=PA11&dq=patent+5051885&hl=en&sa=X&ei=Zar4TuaNB8KksQLOkNXXAQ&ved=0CDMQ6AEwAA
>>
We liked our Apollo Computer DN10K's, too bad about the BiN designed FPU, is this what doomed it? Did they ever fix the bug with the FPU losing accuracy during task switching?
The climate change researcher at our university hated that every run of his model gave a different result on the DN10k. Garbage in garbage out I say.
The same code compiled for Cray also gave results he did not like. ;)
I would like a copy of the instruction set, is it available?