Article: AMD's Mobile Strategy
By: Michael S (already5chosen.delete@this.yahoo.com), December 22, 2011 12:12 am
Room: Moderated Discussions
Wilco (Wilco.Dijkstra@ntlworld.com) on 12/21/11 wrote:
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>You meant "4B/clk copy because its L1D is capable of max 8B/clk load/store".
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I was under impression that Cortex-A9 L1D$ has 128b data path to core. If data path is twice narrower then I take everything I told above back.
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>
>You meant "4B/clk copy because its L1D is capable of max 8B/clk load/store".
>
I was under impression that Cortex-A9 L1D$ has 128b data path to core. If data path is twice narrower then I take everything I told above back.
