Article: AMD's Mobile Strategy
By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), December 22, 2011 6:20 am
Room: Moderated Discussions
Michael S (already5chosen@yahoo.com) on 12/22/11 wrote:
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>Wilco (Wilco.Dijkstra@ntlworld.com) on 12/21/11 wrote:
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>>You meant "4B/clk copy because its L1D is capable of max 8B/clk load/store".
>>
>
>I was under impression that Cortex-A9 L1D$ has 128b data path to core. If data
>path is twice narrower then I take everything I told above back.
No, if you look at the vldm/vstm cycle timings on page 38 of http://infocenter.arm.com/help/topic/com.arm.doc.ddi0409g/DDI0409G_cortex_a9_neon_mpe_r3p0_trm.pdf you can see it does 64-bits per cycle.
It does support a dual 64-bit interface to L2, but they are fixed to the i-side and d-side, you at best you get 64-bits per cycle data bandwidth.
Wilco
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>Wilco (Wilco.Dijkstra@ntlworld.com) on 12/21/11 wrote:
>---------------------------
>>
>>You meant "4B/clk copy because its L1D is capable of max 8B/clk load/store".
>>
>
>I was under impression that Cortex-A9 L1D$ has 128b data path to core. If data
>path is twice narrower then I take everything I told above back.
No, if you look at the vldm/vstm cycle timings on page 38 of http://infocenter.arm.com/help/topic/com.arm.doc.ddi0409g/DDI0409G_cortex_a9_neon_mpe_r3p0_trm.pdf you can see it does 64-bits per cycle.
It does support a dual 64-bit interface to L2, but they are fixed to the i-side and d-side, you at best you get 64-bits per cycle data bandwidth.
Wilco
