Article: AMD's Mobile Strategy
By: mpx (mpx.delete@this.nomail.pl), December 17, 2011 6:20 am
Room: Moderated Discussions
anon (anon@anon.com) on 12/16/11 wrote:
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>That means the same core can be used for server and client, and also the core can
>run *real* server work (not just partitioned tpcc) well too.
>
In the future there will be more transistors at disposal (process technology going forward), but the same or even lower (economy, growing prices of energy sources) power budgets. This does not bode well for universal cores.
Hybrid CPUs look better. By hybrid I mean both various types of cores optimal for various types of tasks, as well as lots of accelerators. This way for a given task done only processing elements that do it optimally will run it, the rest will be turned off or slowed down to keep power low.
Eg. for encryption, compression, transcoding - mostly acclelerators, for troughput optimizing codes - throughput cores (lots of narrow ones with hordes of threads), for single-thread dependant cores - fewer larger cores will be awakend. For array operations GPGPU portions of chips could be used.
---------------------------
>That means the same core can be used for server and client, and also the core can
>run *real* server work (not just partitioned tpcc) well too.
>
In the future there will be more transistors at disposal (process technology going forward), but the same or even lower (economy, growing prices of energy sources) power budgets. This does not bode well for universal cores.
Hybrid CPUs look better. By hybrid I mean both various types of cores optimal for various types of tasks, as well as lots of accelerators. This way for a given task done only processing elements that do it optimally will run it, the rest will be turned off or slowed down to keep power low.
Eg. for encryption, compression, transcoding - mostly acclelerators, for troughput optimizing codes - throughput cores (lots of narrow ones with hordes of threads), for single-thread dependant cores - fewer larger cores will be awakend. For array operations GPGPU portions of chips could be used.
