mpx (mpx@nomail.pl) on 12/18/11 wrote:
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>anon (anon@anon.com) on 12/17/11 wrote:
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>
>>I'm talking about the general-purpose compute core for high performance server/client workloads, of course.
>>
>>Even if you drop the client part of it, server is still far from EP, so SMT approach
>>is superior to lots of small cores, IMO.
>
>SMT is orthogonal to lots of small cores. You can have lots of small cores with
>SMT (Sparc T3) or low number of large cores without it (Phenom, Core i5 2500).
>
>What you are talking about is CPU composed of duplicated hyperuniversal cores vs. hybrid approach + acceleators.

No, it is not what I'm talking about. Of course SMT is orthogonal to lots of small cores, so I'm not using accurate terminology. From the context I thought it was clearer than it evidently is. I'm talking about partitioning of many resources like BD (the example was L1 cache), versus SMT and fat cores that Intel and IBM have.

And what I'm saying is not absolute or apply to every situation. But the case of L1 caches in BD versus SB and POWER7.

>
>Accelerators are done deal. All large companies use them or plan to use them. Oracle
>for cryptography, Apple has OpenCL in every Mac, AMD promotes APUs, IBM is expected
>to include them in Power7+, while already having them in Wire-Speed processor. Intel
>is not very enthusiastic, but still does transcoding accelerator an provides OpenCL
>for Macs. Microsoft has always provided ways to acceleratr graphics operations (2D,
>3D, video), now it promotes DX11 compute.
>
>Differentiated cores did not yet appear, but I find it likely that with larger
>transistor budgets and power budgets going down this is a valid direction.

I don't know how you read that into it. I really am talking about the general-purpose compute core for high performance server/client workloads.