Article: AMD's Mobile Strategy
By: mpx (mpx.delete@this.nomail.pl), December 17, 2011 3:17 pm
Room: Moderated Discussions
For normal priced desktops:
For notebooks:
AMD offers 2 decoders per processor (Trinity).
Intel offers up to 4 decoders per processors, but most sell with 2 decoders anyway.
For desktops:
AMD offers up 2,3 or 4 doecoders per processor. All options popular.
Intel offers up 2 or 4 decoders for processor. All options popular.
For workstations or high-end PCs:
Intel offers 6 decoders per processor (Core i7 39xx)
AMD is not on this market officially. You can ATX Opteron board for workstation though.
For normal priced servers:
AMD offers up to 8 decoders per processor (Opteron 62xx)
Intel offers up to 8 decoders per processor (Xeon E5).
For large memory (expansive) servers:
Intel offers 10 decoders per processor, with no AVX instructions (Xeon E7)
AMD offers 8 decoders per processor.
If you count the number of decoders you get per particular price point - this is quite even.
-------------------
When it comes to L0 caches for instructions you really need to appreciate RISC advantage. L0 cache in Snapdragon S4 is just a piece of direct-mapped cache.
http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2
No need for complicated schemes to map real addresses to microops adresses or deal with instructions that decode into too much micro-ops to fit in cache. Basically low latency for free.
For notebooks:
AMD offers 2 decoders per processor (Trinity).
Intel offers up to 4 decoders per processors, but most sell with 2 decoders anyway.
For desktops:
AMD offers up 2,3 or 4 doecoders per processor. All options popular.
Intel offers up 2 or 4 decoders for processor. All options popular.
For workstations or high-end PCs:
Intel offers 6 decoders per processor (Core i7 39xx)
AMD is not on this market officially. You can ATX Opteron board for workstation though.
For normal priced servers:
AMD offers up to 8 decoders per processor (Opteron 62xx)
Intel offers up to 8 decoders per processor (Xeon E5).
For large memory (expansive) servers:
Intel offers 10 decoders per processor, with no AVX instructions (Xeon E7)
AMD offers 8 decoders per processor.
If you count the number of decoders you get per particular price point - this is quite even.
-------------------
When it comes to L0 caches for instructions you really need to appreciate RISC advantage. L0 cache in Snapdragon S4 is just a piece of direct-mapped cache.
http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2
No need for complicated schemes to map real addresses to microops adresses or deal with instructions that decode into too much micro-ops to fit in cache. Basically low latency for free.