Article: AMD's Mobile Strategy
By: Eugene Nalimov (enal.delete@this.google.dot.com), December 16, 2011 11:07 am
Room: Moderated Discussions
Wilco (Wilco.Dijkstra@ntlworld.com) on 12/16/11 wrote:
---------------------------
>[...]
>>x86 instructions do more.
>No, on average they do less. Nobody cares what the most
>complex instructions can do if they never get used by the compiler.
>And x86 instructions are just not a good fit for the code that most
>people write.
That could be true in the past, but starting from past-Pentium4 compilers are emitting complex code again. At least Visual C does that. I worked in the Visual C compiler back-end for lot of years, and have first-hand knowledge.
Several years ago x86 Visual C back-end still tried to emit code that would work reasonable well on Pentium 4, but x64 Visual C fully used abilities of Opterons and post-Pentium 4 CPUs. Last work I did at the Visual C was to share some of those optimizations with x86-targeting back-end.
>[...]
>Show an example where an x86 addressing mode replaces 2 or more
>ARM instructions.
mov reg1, imm[reg2+reg3]
>[...]
>How many x86 micro ops do you need to execute this single
>ARM instruction:
>addeq r0,r1,r2,lsl #2>
Probably 2?
jnz L1
lea r0,[r2+r3*4]
L1:
From what I heard, compilers targeting newest ARM micro-architectures prefer not to use conditional execution as well... :-(
>[...]
>Immediates are not really a problem on ARM [...]
People working on ARM-targeting JIT have different opinion. (No, that's not me, in my current company I have nothing to do with compilers/JIT-ters...)
Thanks,
Eugene
---------------------------
>[...]
>>x86 instructions do more.
>No, on average they do less. Nobody cares what the most
>complex instructions can do if they never get used by the compiler.
>And x86 instructions are just not a good fit for the code that most
>people write.
That could be true in the past, but starting from past-Pentium4 compilers are emitting complex code again. At least Visual C does that. I worked in the Visual C compiler back-end for lot of years, and have first-hand knowledge.
Several years ago x86 Visual C back-end still tried to emit code that would work reasonable well on Pentium 4, but x64 Visual C fully used abilities of Opterons and post-Pentium 4 CPUs. Last work I did at the Visual C was to share some of those optimizations with x86-targeting back-end.
>[...]
>Show an example where an x86 addressing mode replaces 2 or more
>ARM instructions.
mov reg1, imm[reg2+reg3]
>[...]
>How many x86 micro ops do you need to execute this single
>ARM instruction:
>addeq r0,r1,r2,lsl #2>
Probably 2?
jnz L1
lea r0,[r2+r3*4]
L1:
From what I heard, compilers targeting newest ARM micro-architectures prefer not to use conditional execution as well... :-(
>[...]
>Immediates are not really a problem on ARM [...]
People working on ARM-targeting JIT have different opinion. (No, that's not me, in my current company I have nothing to do with compilers/JIT-ters...)
Thanks,
Eugene