Paul A. Clayton (paaronclayton@gmail.com) on 12/15/11 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 12/15/11 wrote:
>---------------------------
>[snip]
>>Hrmm, what do you mean? AMD's architecture is more efficient in terms of perf/W
>>and perf/area, so I don't see any reason for them to give up that advantage.
>
>I was under the impression that AMD's next generation GPU
>ISA is less efficient in terms of peak performance than the
>current ISA. I.e., they chose to trade the potential
>efficiency of VLIW for the compiler-friendliness of a more
>RISC-like ISA.
>
>Or am I misremembering or misinterpreting?
>
>The above would imply that programmability was viewed as
>more important than performance per Watt or per cm².

Actually, it seems to be the opposite, because VLIW gets
replaced with running more threads at once, which guarantees
a higher throughput independent from the amount of
instructions in a single VLIW and looks less complex to
implement in silicon.

AND it gives the well known advantage of simpler compilers.