Article: AMD's Mobile Strategy
By: Rohit (.delete@this..), December 15, 2011 9:09 pm
Room: Moderated Discussions
Paul A. Clayton (paaronclayton@gmail.com) on 12/15/11 wrote:
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>David Kanter (dkanter@realworldtech.com) on 12/15/11 wrote:
>---------------------------
>[snip]
>>Hrmm, what do you mean? AMD's architecture is more efficient in terms of perf/W
>>and perf/area, so I don't see any reason for them to give up that advantage.
>
>I was under the impression that AMD's next generation GPU
>ISA is less efficient in terms of peak performance than the
>current ISA. I.e., they chose to trade the potential
>efficiency of VLIW for the compiler-friendliness of a more
>RISC-like ISA.
>
>Or am I misremembering or misinterpreting?
>
>The above would imply that programmability was viewed as
>more important than performance per Watt or per cm2.
It's less efficient with respect to VLIW4 in some ways but better in others. On the surface, it still seems to be quite a bit better than Fermi architecture.
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>David Kanter (dkanter@realworldtech.com) on 12/15/11 wrote:
>---------------------------
>[snip]
>>Hrmm, what do you mean? AMD's architecture is more efficient in terms of perf/W
>>and perf/area, so I don't see any reason for them to give up that advantage.
>
>I was under the impression that AMD's next generation GPU
>ISA is less efficient in terms of peak performance than the
>current ISA. I.e., they chose to trade the potential
>efficiency of VLIW for the compiler-friendliness of a more
>RISC-like ISA.
>
>Or am I misremembering or misinterpreting?
>
>The above would imply that programmability was viewed as
>more important than performance per Watt or per cm2.
It's less efficient with respect to VLIW4 in some ways but better in others. On the surface, it still seems to be quite a bit better than Fermi architecture.