Megol (golem960@gmail.com) on 12/17/11 wrote:
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>Michael S (already5chosen@yahoo.com) on 12/17/11 wrote:
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>>Dan Fay (daniel.fay@gmail.com) on 12/16/11 wrote:
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>>>>Regrettably, AMD could have been a contendah if their CPU core design had been
>>>>a performer. (When will these companies learn that long pipe, high frequency hot
>>>>rod designs are more hot than rod? AMD made a killing off the Pentium 4!) They
>>>>were strategically the best placed among Intel / AMD / NVidia to capture the portable
>>>>market. I don't think another opportunity like that is going to come for a while.
>>>
>>>What would AMD really bring to the table here? Lots of SoC companies (Samsung,
>>>TI, Marvell) make very competitive designs just licensing cores (e.g. Cortex-A8/A9)
>>>from ARM. Qualcomm does their own processor designs, but does it really give them a big leg up in the marketplace?
>>>
>>
>>Nitpick: leading Cortex-A licensees are (Samsung, Apple, TI, Freescale). NVidia
>>is likely #5 but very far behind. Soon we will see Altera in the list, that should surpass NVidia in no time.
>>Marvell, like Qualcomm, uses cores of their own. In fact, Marvell target slightly
>>different, and probably broader, market than the other 5.
>>
>>>Even if AMD could get a significant, say 20-30% processor core power improvement
>>>out of an ARM design, I'm not sure how much of a real competitive advantage that
>>>would be, since the "rest of the system" consumes the lion's share of power.
>>>
>>>So the only other possible advantage AMD might have is their graphics division.
>>>Here, the question is, can they scale down their GPU designs to the low-power,
>>>low memory bandwidth constraints inherent to tablets and smartphones? Imagination's
>>>PowerVR designs might have an inherent advantage here because of their tile-based deferred rendering.
>>>
>>>IIRC, Bobcat has 16 pipeline stages, while the Cortex-A8 has 13 and the Cortex-A15
>>>has 15 stages, so it's not that out of line with the competition.

It's 8 for Cortex-A9, and 15 for Bobcat and A15. The pipeline length one considers is the branch mispredict penalty as that gives an accurate picture of fetch/decode/issue/execute stages required for simple integer instructions.

>>I don't know why you find pipeline stages trivia relevant. If we are going to believe
>>to geekmarks, Bobcat is good deal faster than Cortex-A9 clock for clock, although
>memory subsystems are far from equal.
>>
>Pipeline stages can be used to compare architectures, with the higher clockrates
>of Bobcat it's an indication that x86 doesn't require too much complexity compared to ARM.

That theory fails if you consider the facts: currently shipping silicon is at 1.4GHz for A9 vs 1.65GHz for Bobat. Note the A9 is hardly maxed out with 1.8GHz variants coming soon. Have any faster Bobcats been announced for 2012? I couldn't find any. So the fact that Bobcat needs almost double the number of pipeline stages is an indication that x86 is a lot more complex.

>Aren't both Apple A5* vs. Any Bobcat 64 bits with ~the memory clock, DDR2 for A5 and DDR3 for Bobcat?

It's DDR2-400 vs DDR3-1333 (though low-end models are DDR3-1066), that's quite a lot more bandwidth.

Wilco