iz (i@z.x) on 12/20/11 wrote:
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>David Hess (davidwhess@gmail.com) on 12/20/11 wrote:
>---------------------------
>>How much does the tester time cost? At one time the number of pins on the IC package
>>primarily determined the cost. Later the most expensive part was the tester time
>>and for some ICs the tester time is still the most expensive part.
>>
>>Testing and verifying a high capacity flash chip through that narrow and slow interface does not sound cheap.
>
>They can test a lot of chips at the same time though,
>they can send the same commands and data to all of them.
>Only at verification time do they need to read from
>individual chips. So overall the narrow interface seems
>more like an advantage. I think the main limitation is
>the flash write/erase speed, not the interface.

The slow internal write and erase speeds are going to add significantly to test time. Even RAM testing is limited by this and they are a lot faster.

>They only really test a few spread out sample blocks to
>check for endurance and error rates, which they mark as
>invalid when done. There is no need to check all blocks
>because they can be checked when actually written to, and
>supposedly the chips are regular enough that the quality
>doesn't vary that much. Big defects are detected at write
>time, small defects are covered by ECC.

All of the Flash datasheets I have read indicated that they come from the factory with a programmed bad block list. Maybe the devices intended for SSD use leave that out though to lower costs.