Article: AMD's Mobile Strategy
By: Ungo (a.delete@this.b.c.d.e), December 20, 2011 6:36 pm
Room: Moderated Discussions
David Hess (davidwhess@gmail.com) on 12/20/11 wrote:
---------------------------
>How much does the tester time cost? At one time the number of pins on the IC package
>primarily determined the cost. Later the most expensive part was the tester time
>and for some ICs the tester time is still the most expensive part.
>
>Testing and verifying a high capacity flash chip through that narrow and slow interface does not sound cheap.
I suspect the interface is not the limiting factor for flash. A functional test of the memory array would require writing data, verifying it, erasing it, and finally verifying the erase. The only steps where interface performance should be a limit are the verification passes, but I'd expect the other two steps to dominate test time. Writes are slow (especially MLC (*)), and erase is glacial.
* - My complete-outsider's understanding is that to compensate for bit cell aging and process variation, the MLC write algorithm is a loop: inject a small amount of charge into the floating gate, perform a read to see how much charge got injected, repeat until the gate is charged to the correct level. SLC flash write is cruder and faster because it only has to program binary values into the cell. I welcome correction from anyone with firsthand knowledge!
---------------------------
>How much does the tester time cost? At one time the number of pins on the IC package
>primarily determined the cost. Later the most expensive part was the tester time
>and for some ICs the tester time is still the most expensive part.
>
>Testing and verifying a high capacity flash chip through that narrow and slow interface does not sound cheap.
I suspect the interface is not the limiting factor for flash. A functional test of the memory array would require writing data, verifying it, erasing it, and finally verifying the erase. The only steps where interface performance should be a limit are the verification passes, but I'd expect the other two steps to dominate test time. Writes are slow (especially MLC (*)), and erase is glacial.
* - My complete-outsider's understanding is that to compensate for bit cell aging and process variation, the MLC write algorithm is a loop: inject a small amount of charge into the floating gate, perform a read to see how much charge got injected, repeat until the gate is charged to the correct level. SLC flash write is cruder and faster because it only has to program binary values into the cell. I welcome correction from anyone with firsthand knowledge!
