Ungo (a@b.c.d.e) on 12/20/11 wrote:
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>David Hess (davidwhess@gmail.com) on 12/20/11 wrote:
>---------------------------
>>How much does the tester time cost? At one time the number of pins on the IC package
>>primarily determined the cost. Later the most expensive part was the tester time
>>and for some ICs the tester time is still the most expensive part.
>>
>>Testing and verifying a high capacity flash chip through that narrow and slow interface does not sound cheap.
>
>I suspect the interface is not the limiting factor for flash. A functional test
>of the memory array would require writing data, verifying it, erasing it, and finally
>verifying the erase. The only steps where interface performance should be a limit
>are the verification passes, but I'd expect the other two steps to dominate test
>time. Writes are slow (especially MLC (*)), and erase is glacial.

Parts like RAM usually have extensive built in self testing functionality which the external tester takes advantage of. I guess with Flash the slow write and erase times are going to be a bigger problem than the slow interface.

>* - My complete-outsider's understanding is that to compensate for bit cell aging
>and process variation, the MLC write algorithm is a loop: inject a small amount
>of charge into the floating gate, perform a read to see how much charge got injected,
>repeat until the gate is charged to the correct level. SLC flash write is cruder
>and faster because it only has to program binary values into the cell. I welcome
>correction from anyone with firsthand knowledge!

I generally do something similar for my EEPROM programming routines. The options are generally to program for a fixed time or until all bits verify correct and then over-program for some percentage of that time again. The later can extend EEPROM life by not programming or erasing more than necessary. As the cells age, the programming and erase times go up which can help with reliability if you take advantage of the knowledge.