Bill Henkel wrote:
> Another differentiator could be enabling 3rd-party
> innovation by making the cache-coherency protocol on the
> HyperTransport bus publically available and royalty-free.

David Kanter responded:
> How would that help?

It would make it possible for 3rd parties to make cache-coherent hardware accelerators for systems with AMD processors. This can't be done on systems with Intel processors because PCI Express doesn't suppport it. Another application would be to connect an FPGA to the HyperTransport bus of an AMD processor and have the FPGA multiplex/demultiplex it to multiple HyperTransport busses. This would allow system vendors to make bigger cache-coherent systems with AMD processors than Intel processors. Another application would be to increase the amount of DRAM in a system by connecting the HyperTransport bus to an FPGA and have the FPGA drive multiple DRAM channels. The latency would not be as low as DRAM connected to the processor but it would be a lot better than SSD or hard disk.