Article: AMD's Mobile Strategy
By: David Kanter (dkanter.delete@this.realworldtech.com), December 30, 2011 9:34 pm
Room: Moderated Discussions
Bill Henkel (noemail@yahoo.com) on 12/30/11 wrote:
---------------------------
>There must be some people that need more CPU performance, >otherwise all PC sales in the developed world would stop.
>
>I'd like to clarify my suggestion of adding 128 MBytes or 256 MBytes of L4 cache
>to the processor package. The physical size of the processor package is determined
>by the number of pins. There is plenty of space to put 4 or 8 cache die on the
>same substrate that the processor die is attached to.
>The Pentium Pro had something
>like this years ago but it used wire bonding instead of a >flip-chip attach.
That's true, but Intel stopped doing that as soon as they could.
IBM does that for some of their high-end systems. It takes pins though and costs power.
>An
>alternative would be to stack the cache die on top of the >processor die using through
>silicon vias. I think that is what David Kanter means by "3D integration".
Yes. The yields aren't there yet for TSVs.
>I bet
>with $100 of cost in cache chips, they could sell such a >processor for an extra $500.
The problem is that the cost is not just extra chips. It's cooling, testing, yields, etc.
On top of that, you use more die area on the main SoC for the L4 interface. TSVs impact die area as well (not to mention yield).
The biggest problem is that the economics totally break for AMD when you are talking about using a different die for servers. Intel has enough volume they can afford to do server chips, although you'll notice they re-use the cores and many other components. AMD doesn't have enough volume at all, so it's very difficult to amortize the R&D costs.
The bottom line is that I agree it would be a nice differentiator. However, I don't think it can be done in an economically viable fashion today, and when it is feasible, it will feasible for both Intel and AMD.
David
---------------------------
>There must be some people that need more CPU performance, >otherwise all PC sales in the developed world would stop.
>
>I'd like to clarify my suggestion of adding 128 MBytes or 256 MBytes of L4 cache
>to the processor package. The physical size of the processor package is determined
>by the number of pins. There is plenty of space to put 4 or 8 cache die on the
>same substrate that the processor die is attached to.
>The Pentium Pro had something
>like this years ago but it used wire bonding instead of a >flip-chip attach.
That's true, but Intel stopped doing that as soon as they could.
IBM does that for some of their high-end systems. It takes pins though and costs power.
>An
>alternative would be to stack the cache die on top of the >processor die using through
>silicon vias. I think that is what David Kanter means by "3D integration".
Yes. The yields aren't there yet for TSVs.
>I bet
>with $100 of cost in cache chips, they could sell such a >processor for an extra $500.
The problem is that the cost is not just extra chips. It's cooling, testing, yields, etc.
On top of that, you use more die area on the main SoC for the L4 interface. TSVs impact die area as well (not to mention yield).
The biggest problem is that the economics totally break for AMD when you are talking about using a different die for servers. Intel has enough volume they can afford to do server chips, although you'll notice they re-use the cores and many other components. AMD doesn't have enough volume at all, so it's very difficult to amortize the R&D costs.
The bottom line is that I agree it would be a nice differentiator. However, I don't think it can be done in an economically viable fashion today, and when it is feasible, it will feasible for both Intel and AMD.
David
