David Kanter wrote:
> So are you going to have a separate CPU die for low-end desktops (no L4),
> high-end desktops (small L4) and servers (big L4)? If so, now
> your validation is 3X worse because you have 3 models. And
> each separate die will need masks (probably $1-2M/each).

There should be 3 separate die. Each of these markets is billions of dollars per year so a company that is going to be successful in these markets can afford the validation and mask costs.

David Kanter wrote:
> How many of these do you think AMD can sell, and how
> much do you think they can increase their prices by?

I think $100-$150 would be a reasonable price premium for a high-end desktop chip. A server chip with a big L4 cache could get a $500 price premium. For every X% increase in single thread performance compared to the competition, I think 2X% increase in price is reasonable. I think a processor without an L4 cache won't be considered a high-end processor at some point. If AMD wants their entire microprocessor product line to be low-profit, bargain bin chips, there is certainly no reason for them to have any L4 cache.

David Kanter wrote:
> How much do you think each of those chips is going to cost?

If a high-end desktop processor had 2 cache chips and a server processor had 8 cache chips, I think $10-$20 of cost per cache chip would be about right. The cost of assembly and the cost of the substrate in the package are minimal. Flip-chip assembly is very mature so assembly should not be a yield problem.

Paul A. Clayton wrote:
> Unfortunately, I do not think AMD is positioned to lead in the
> re-introduction of off-chip cache. The learning curve for MCM fabrication
> might excessively penalize their smaller production volume.

The substrate in the package is just a small FR4 printed circuit board, not a fancy ceramic MCM. Almost every BGA package made today contains one. These substrates are fabricated by board shops, not semiconductor companies, and they are readily available today.

Paul A. Clayton wrote:
> It is not clear that pure SRAM would be better than DRAM or a
> DRAM/SRAM hybrid in terms of capacity and power efficiency.

David Kanter wrote:
> Yeah, I think DRAM makes more sense too.

I like DRAM because of its lower cost per bit but I wonder if DRAM cells will leak too much if they are near a hot processor. The refresh period could be shortened and maybe there is some way to design a DRAM cell that doesn't leak so much when it gets hot. As for the latency of DRAM, I think that can be solved by keeping the bit lines and word lines short, which means lots of small arrays instead of a few big arrays.