Paul A. Clayton (paaronclayton@gmail.com) on 1/6/12 wrote:
---------------------------
>Bill Henkel (noemail@yahoo.com) on 1/5/12 wrote:
>---------------------------
>[snip]
>>Paul A. Clayton wrote:
>>> Unfortunately, I do not think AMD is positioned to lead in the
>>> re-introduction of off-chip cache. The learning curve for MCM fabrication
>>> might excessively penalize their smaller production volume.
>>
>>The substrate in the package is just a small FR4 printed
>>circuit board, not a fancy ceramic MCM. Almost every BGA
>>package made today contains one. These substrates are
>>fabricated by board shops, not semiconductor companies,
>>and they are readily available today.
>
>Do you happen to know what the cost, bandwidth, and
>(perhaps even) power differences are between different
>types of integration? While BGA technology is mature, I
>was under the impression that silicon interposer was
>progressing the learning curve rather quickly now and
>provides much better bandwidth per area of interface at
>projected reasonable incremental cost (once reasonably
>mature).

>By the way, would it be practical to use a small portion
>of the silicon interposer 'chip' for I/O interfaces (using
>a simple, full depreciated process technology--I receive
>the impression that at least some I/O interfaces do not
>benefit from smaller transistors)? Presumably the
>"stepper" would be more of a 'leaper' (skipping over area
>that is just for the interposer), though there might be
>some advantage to simple amplification and switching for
>the interposer function. The economics of such might
>work out (though I am sceptical).

Silicon interposers are generally not used for active circuits, to avoid problems with the TSVs. People definitely contemplate using the area for passives, but if you want transistors...then it's full 3D, not an interposer.

Of course, the whole point of an interposer is to avoid any yield issues related to TSVs being near to transistors and to simplify testing.

David