Mark Roulo (nothanks@xxx.com) on 1/9/12 wrote:
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>David Kanter (dkanter@realworldtech.com) on 1/6/12 wrote:
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>>Silicon interposers are generally not used for active circuits, to avoid problems
>>with the TSVs. People definitely contemplate using the area for passives, but if
>>you want transistors...then it's full 3D, not an interposer.
>>
>>Of course, the whole point of an interposer is to avoid any yield issues related
>>to TSVs being near to transistors and to simplify testing.
>>
>
>The Xilinx Virtex-7 uses one of these passive interposer >thingies to connect different
>dies filled with FPGA logic. Why would this not work to >connect a CPU die with a DRAM?

Yes, you can. I think for DRAM, the issue is cooling (due to leakage sensitivity), extra CPU pins for the interface, proper CPU architecture to take advantage of the DRAM and ecosystem readiness. E.g. TSMC seems to have shifted strategies for their 3D, and it appears to be more restrictive for customers than prior plans.

Xilinx is really one of the first to be using interposers, so it's still new. We will definitely see wider usage, but it takes time. I think their motivation was building a 'big' FPGA out of smaller, cutting edge chips. So it gets around the problems of yield/variability for a big die on a new process.

FWIW, there were some other FPGA companies doing interesting stuff with stuff with 3D/2.5D.

David