>The economics don't make sense. As I mentioned in another post, that means you need:
>
>1. An L4 cache controller
>
>2. Pins to connect to the L4 cache, with sufficient bandwidth to handle snooping traffic in servers
>
>The controller and pins use up substantial extra die area and power. So are you
>going to have a separate CPU die for low-end desktops (no L4), high-end desktops (small L4) and servers (big L4)?
>
>If so, now your validation is 3X worse because you have 3 models. And each separate
>die will need masks (probably $1-2M/each).
>
>If you use the same die, then you are wasting significant power and area on the
>high volume (low-end desktops), to improve things for relatively low volume parts (high-end desktop and server).
>
>How many of these do you think AMD can sell, and how much do you think they can increase their prices by?
>
>Let's just recap the costs:
>
>1. More die area for L4 controller
>2. More die area for pins
>3. More validation for different models
>4. External SRAM chips (how much would a 32MB SRAM cost?)
>5. More complex packaging, lower total yields
>6. Need to design a new snoop filter to deal with larger cache sizes in servers
>
>Those costs are pretty significant.

What I could see as possibly more realistic is for AMD to provide a fast, local DRAM memory in the neighborhood of 256-512MB (perhaps something like GDDR5) on its processors to improve embedded GPU performance. This memory could then be repurposed on servers and/or HPC systems as a high-speed, local, general-purpose memory.