Ricardo B (ricardo.b@xxxxx.xx) on 1/4/12 wrote:
---------------------------
>Bill Henkel (noemail@yahoo.com) on 1/3/12 wrote:
>---------------------------
>>Ricardo B on 12/31/11 wrote:
>>> if the L4 is going to be SRAM (although such huge sizes are not
>>> realistic for SRAM) and you need a separate die for the L4 models, it
>>> would be better to put the L4 cache itself the same die as the CPU.
>>
>>The cache chips could be SRAM with 32 MBytes per chip. I don't think its possible to put 8 * 32 MBytes = 256 MBytes
>>on the processor die any time soon.
>
>True, a single 32 MB SRAM would be some 500 mm², making a huge chip by itself.

At 32nm? Are you sure? I'd expect less than 200 mm^2.

>Putting 8 of those in a single chip is simply not possible with.

For applications that are not I/O or VCC/GND bound, I thing it is possible to pack 8x200 mm^2 dies into 2500 to 3000 mm^2 MCM, i.e. ~ the same size as AMD Socket G34.

The problem is - the latency would be, may be, 1.5 times better than main memory in single-socket configuration. So, it almost for sure not worth the trouble in 1-2 socket configurations. As to 4-8 sockets, if you are going to increase your CPU pin count then it could be preferable, instead of spending them to L4 cache, to add few more inter-processor links or memory channels.

>
>However, even spread by 8 chips, that a lot of sillicon and a lot of power· That's
>why I said that 256 MB of SRAM cache isn't feasible right now.
>Even IBM had to bite the bullet and use eDRAM as off-chip L3 cache in their POWER systems.
>

Not in the latest one.
I am not aware of any off-chip L3 or L4 cache in Power7-based servers. Just 32 MB on-die eDRAM L3.
May be, you are thinking about z196? Indeed, it uses off-die L4 cache. However, it is not private to particular CPU, but shared by all CPUs in the MCM.