Article: AMD's Mobile Strategy
By: Ricardo B (ricardo.b.delete@this.xxxxx.xxxx), January 6, 2012 5:06 am
Room: Moderated Discussions
Michael S (already5chosen@yahoo.com) on 1/5/12 wrote:
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>The problem is - the latency would be, may be, 1.5 times better than main memory
>in single-socket configuration. So, it almost for sure not worth the trouble in
>1-2 socket configurations. As to 4-8 sockets, if you are going to increase your
>CPU pin count then it could be preferable, instead of spending them to L4 cache,
>to add few more inter-processor links or memory channels.
Single socket latency DRAM is in the 40-50 ns range nowadays.
10 ns or less seems quite feasible with SRAM through a parallel interface.
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>The problem is - the latency would be, may be, 1.5 times better than main memory
>in single-socket configuration. So, it almost for sure not worth the trouble in
>1-2 socket configurations. As to 4-8 sockets, if you are going to increase your
>CPU pin count then it could be preferable, instead of spending them to L4 cache,
>to add few more inter-processor links or memory channels.
Single socket latency DRAM is in the 40-50 ns range nowadays.
10 ns or less seems quite feasible with SRAM through a parallel interface.
