Ricardo B (ricardo.b@xxxxx.xx) on 1/4/12 wrote:
---------------------------
>Bill Henkel (noemail@yahoo.com) on 1/3/12 wrote:
>---------------------------
>>Ricardo B on 12/31/11 wrote:
>>> if the L4 is going to be SRAM (although such huge sizes are not
>>> realistic for SRAM) and you need a separate die for the L4 models, it
>>> would be better to put the L4 cache itself the same die as the CPU.
>>
>>The cache chips could be SRAM with 32 MBytes per chip. I don't think its possible to put 8 * 32 MBytes = 256 MBytes
>>on the processor die any time soon.
>
>True, a single 32 MB SRAM would be some 500 mm², making a huge chip by itself.
>Putting 8 of those in a single chip is simply not possible with.
>
>However, even spread by 8 chips, that a lot of sillicon and a lot of power· That's
>why I said that 256 MB of SRAM cache isn't feasible right now.
>Even IBM had to bite the bullet and use eDRAM as off-chip L3 cache in their POWER systems.
>

Your numbers seem off. Poulson has 32MB of L3, and that's not including L1, L2, and directory cache; if I recall, it adds up to well over 40MB. Poulson is between 500mm^2 and 600mm^2, and that's including both SRAM and cores.