Gregory (gregory2012@gmail.com) on 1/12/12 wrote:
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>You wouldn't reuse the design for a car engine in a train just because "design reuse
>seems like a good thing". Similarly, you can't expect to have an optimal design
>if you reuse the same processor core in a notebook chip (Sandy Bridge) and a server
>chip (Sandy Bridge-EP). The complexity of x86 is forcing this design reuse.


I suspect a significant part of the motivation for design
reuse is from the complexity of an aggressive
high-performance implementation. While IBM's PowerPC 970
was not a simple reuse of POWER4, it was not a major
redesign either. Because POWER4 did not support Altivec
or, IIRC, 32-bit mode, some changes would be necessary.
While the target market for the PowerPC 970 was smaller
than Intel's notebook market, there is not that much
benefit from a major redesign.

Both server and laptop chips will be oriented toward
greater power efficiency while maintaining high performance.
(Interestingly, both would probably also benefit from
larger on-chip caches--servers having workloads that tend
to benefit more from such and laptops because an on-chip
access is so much more power efficient than an off-chip
access.)

I suspect much of the complexity of x86 would be difficult
to handle for a new-comer, but Intel (and AMD) have years
of experience and presumably effective validation tools for
x86.