Article: AMD's Mobile Strategy
By: Alex M (adm.delete@this.hotmail.com), January 6, 2012 5:10 am
Room: Moderated Discussions
Paul A. Clayton (paaronclayton@gmail.com) on 1/4/12 wrote:
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>A more attractive alternative (which Intel seems to be
>ignoring) would seem to be heterogeneous multicore.
I think it is a good idea to have both low latency cores (superscalar) and high throughput cores (wide SIMD) in a system. I suspect Intel's version of it will involve weighing down the high throughput cores with all the baggage and complexity of the x86 instruction set, which is a terrible idea. If Windows gets to decide which threads run on which type of core, it will undoubtedly choose the wrong type of core half the time. If the programmer gets to decide which threads run on which type of core then there is no need for the x86 instruction set on the high throughput cores. The high throughput cores can be graphics cores that can also be used for floating-point vector operations.
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>A more attractive alternative (which Intel seems to be
>ignoring) would seem to be heterogeneous multicore.
I think it is a good idea to have both low latency cores (superscalar) and high throughput cores (wide SIMD) in a system. I suspect Intel's version of it will involve weighing down the high throughput cores with all the baggage and complexity of the x86 instruction set, which is a terrible idea. If Windows gets to decide which threads run on which type of core, it will undoubtedly choose the wrong type of core half the time. If the programmer gets to decide which threads run on which type of core then there is no need for the x86 instruction set on the high throughput cores. The high throughput cores can be graphics cores that can also be used for floating-point vector operations.
