Performance analysis laughable

Article: Medfield, Intel's x86 Phone Chip
By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), January 25, 2012 8:18 am
Room: Moderated Discussions
none (none@arm.com) on 1/25/12 wrote:
---------------------------
>Wilco (Wilco.Dijkstra@ntlworld.com) on 1/25/12 wrote:
>---------------------------
>[...]
>>Running micro benchmarks like Dhrystone/CoreMark gives close to maximum power consumption.
>
>Hu? Neither of them makes use of floating-point or SIMD
>(unless you have strcmp implemented as SIMD instructions in
>your C lib). Neither of them have heavy miss traffic.
>Neither of them completely kill branch predicition. So how
>could they represent maximum power consumption on anything
>but a cache-less, FP-less, bpred-less CPU?

When a core is stalled on memory, it actually uses very little power due to extensive clock gating. With heavy branch misprediction you flush the pipeline all the time, which means you have only executed some of the fetched instructions. Very branchy but well predicted code would do the same number of fetches but execute far more instructions, thus using more power overall.

Old StrongARM figures at http://www.hpl.hp.com/hpjournal/dtj/vol9num1/vol9num1art5.pdf show decode+execute used 26% of total power, while caches used 60%. So getting as many L1 I&D hits as possible was the way to get maximum power. Dhrystone fits that scenario pretty well (note the paper explicitly mentions it is the maximum power consumption case), and I know it was used extensively at ARM for power consumption estimates. You've got a point about VFP/Neon not being used - that would certainly matter if you can issue more instructions after maxing out the L1.

Wilco
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