Performance analysis laughable

Article: Medfield, Intel's x86 Phone Chip
By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), January 26, 2012 6:25 am
Room: Moderated Discussions
observer (no.thanks@for.now) on 1/26/12 wrote:
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>A predicted branch would be predicted either taken or not taken, so fetching would
>start working on either of those paths, right? High performance "deeply" pipelined
>instruction fetch costs power in my experience... not much difference in power for
>correct / incorrect predictions, but correct predictions reduce execution time ->
>lowering the energy consumption for a given task. Could you elaborate why this would
>be very different for the core you had in mind? Disregarding execution unit power that is.

We were discussing max instantaneous power for a CPU, not energy consumption for a given task. It doesn't make sense to talk about maximizing energy use, you'd just turn off the caches... You actually want to minimize the total energy by lowering frequency and voltage to the optimal perf/Watt point (for a low leakage CPU that would typically be its lowest frequency if there is no time limit). That means average power consumption will be extremely low.

To get max power use, you have to maximise the number of transistor switches per cycle, especially the expensive transistors in critical paths such as cache lookup. Stalling a modern CPU doesn't use much power as there are no transistor switches in the majority of the core due to clock gating. Therefore you need to minimize interlocks, branch mispredicts, cachemisses etc. You need a branch every cycle as sequential fetch avoids TLB and cache lookups and just reads the next block from a preselected cacheline.

Wilco
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