Analysis of Haswell's TM online

By: David Kanter (dkanter.delete@this.realworldtech.com), February 15, 2012 5:27 am
Room: Moderated Discussions
Intel's upcoming Haswell microprocessors include transactional memory and hardware lock elision that are exposed through the Transactional Synchronization Extensions or TSX. In this article, I discuss TSX and predict the implementation details of Haswell's transactional memory and expected adoption across the industry, based on my previous experience.

http://www.realworldtech.com/page.cfm?ArticleID=RWT021512050738

I highly recommend this article for anyone with an interest in TM, as I discuss my expectations for how Intel implemented TM and what this means in terms of practical limitations.

David
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TopicPosted ByDate
Analysis of Haswell's TM onlineDavid Kanter2012/02/15 05:27 AM
  Analysis of Haswell's TM onlineMr. Camel2012/02/15 07:02 AM
  Analysis of Haswell's TM onlineFoo_2012/02/15 07:27 AM
    Analysis of Haswell's TM onlineMr. Camel2012/02/15 08:10 AM
      Writeback at first transactional writePaul A. Clayton2012/02/15 08:19 AM
        Writeback at first transactional writeMr. Camel2012/02/15 09:44 AM
    Analysis of Haswell's TM onlineDavid Kanter2012/02/16 03:06 PM
      Analysis of Haswell's TM onlineiz2012/02/17 12:01 AM
        Analysis of Haswell's TM onlineDavid Kanter2012/02/17 01:55 AM
          Analysis of Haswell's TM onlineiz2012/02/17 03:14 AM
            TM not for fine-grained controlPaul A. Clayton2012/02/17 07:15 AM
              Interaction with software TM?Paul A. Clayton2012/02/17 08:35 AM
                Using the branch-predictoriz2012/02/18 04:58 AM
                  Multiple checkpoints and versioningPaul A. Clayton2012/02/18 10:13 AM
                    Multiple checkpoints and versioningiz2012/02/18 09:36 PM
                      Multiple checkpoints and versioningsJ2012/02/19 06:33 AM
                  Using the branch-predictorDavid Kanter2012/02/18 11:14 AM
                    Partial rollbacksPaul A. Clayton2012/02/18 01:09 PM
                    Using the branch-predictoriz2012/02/18 10:19 PM
                  Using the branch-predictorLinus Torvalds2012/02/18 03:24 PM
                    Using the branch-predictorAntti-Ville Tuunainen2012/02/18 06:29 PM
                      Using the branch-predictorLinus Torvalds2012/02/18 07:02 PM
                Interaction with software TM?anonymous2012/02/18 12:08 PM
                  ASF not quite vaporware?Paul A. Clayton2012/02/18 02:06 PM
              TM not for fine-grained controlAntti-Ville Tuunainen2012/02/17 04:16 PM
                Software TMsDavid Kanter2012/02/17 05:19 PM
                  STM not the primary target?Paul A. Clayton2012/02/17 10:56 PM
                Effectively thread-local storagePaul A. Clayton2012/02/17 10:27 PM
              Thanks for the excellent answer!iz2012/02/18 03:52 AM
            Analysis of Haswell's TM onlineDavid Kanter2012/02/17 11:05 AM
              Commit and rollback of a lock within a transaction??Paul A. Clayton2012/02/17 02:51 PM
                Commit and rollback of a lock within a transaction??David Kanter2012/02/17 05:46 PM
                  L2 as a way stationPaul A. Clayton2012/02/17 10:19 PM
                    L2 as a way stationDavid Kanter2012/02/18 02:39 AM
                      L2 as a way stationPaul A. Clayton2012/02/18 11:45 AM
                        L2 as a way stationDavid Kanter2012/02/18 12:12 PM
                          V-way cache topic tangentPaul A. Clayton2012/02/18 01:54 PM
                          L2 as a way stationiz2012/02/18 11:37 PM
  Minor corrections and some commentsPaul A. Clayton2012/02/15 09:23 AM
  Will Haswell ship?Michael S2012/02/15 01:54 PM
    Will Haswell ship?Mark Roulo2012/02/15 02:29 PM
      Like Pentium4 HyperThreadingPaul A. Clayton2012/02/15 03:12 PM
  AMD's exclusive cachesDoug Siebert2012/02/15 03:57 PM
    Exclusivity not a huge problem?Paul A. Clayton2012/02/15 05:27 PM
      AMD's caches 'mostly exclusive'David Kanter2012/02/16 11:36 AM
        Not quite 'by definition'Paul A. Clayton2012/02/16 05:05 PM
    AMD's L3 aren't exclusive... Neither inclusive (NT)EduardoS2012/02/15 06:14 PM
  Analysis of Haswell's TM onlineabc2012/02/15 10:53 PM
    Broken URLs?David Kanter2012/02/16 03:08 PM
      Broken URLs?abc2012/02/18 01:07 AM
  Why is the architectural register state restored?Konard Schwarz2012/02/16 01:42 AM
    Why is the architectural register state restored?sJ2012/02/16 03:13 AM
    Why is the architectural register state restored?Antti-Ville Tuunainen2012/02/16 04:38 AM
    Why is the architectural register state restored?bakaneko2012/02/16 05:01 AM
      Why is the architectural register state restored?bakaneko2012/02/16 09:14 AM
    Why is the architectural register state restored?Robert Davide Graham2012/02/16 12:04 PM
  Questions about TM behaviourEduardoS2012/02/18 05:33 PM
    Questions about TM behaviourDavid Kanter2012/02/18 05:39 PM
      Questions about TM behaviourEduardoS2012/02/18 05:46 PM
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