By: Oliver S. (spiegelneuron.delete@this.gmaill.com), August 13, 2019 12:58 am
Room: Moderated Discussions
There's one mistake in your analysis: The "Intel® 64 and IA-32 Architectures Optimization Reference Manual" says that only the L1-cache tracks the read and written cachelines: "The processor tracks both the read-set addresses and the write-set addresses in the first level data cache (L1 cache) of the processor.". And not L1 / L2.
| Topic | Posted By | Date |
|---|---|---|
| A bit about yourself [OT] | Moritz | 2012/02/26 02:29 AM |
| link | Moritz | 2012/02/26 02:40 AM |
| A bit about yourself [OT] | David Kanter | 2012/02/27 01:40 PM |
| Reply L2 | Moritz | 2012/03/01 02:20 PM |
| A bit about yourself [OT] | lemuel | 2012/05/18 02:22 PM |
| A bit about yourself [OT] | kk | 2013/06/06 02:37 PM |
| A bit about yourself [OT] | Oliver S. | 2019/08/13 12:58 AM |
| A bit about yourself [OT] | David Kanter | 2019/08/13 08:55 AM |