A bit about yourself [OT]

Article: Analysis of Haswell's Transactional Memory
By: David Kanter (dkanter.delete@this.realworldtech.com), August 13, 2019 8:55 am
Room: Moderated Discussions
Oliver S. (spiegelneuron.delete@this.gmaill.com) on August 13, 2019 12:58 am wrote:
> There's one mistake in your analysis: The "Intel® 64 and IA-32 Architectures Optimization
> Reference Manual" says that only the L1-cache tracks the read and written cachelines:
> "The processor tracks both the read-set addresses and the write-set addresses in the
> first level data cache (L1 cache) of the processor.". And not L1 / L2.

Yup. I think the RS/WS tracking also occurs in the line fill buffers, which means that you can track some lines that are not in the L1.

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TopicPosted ByDate
A bit about yourself [OT]Moritz2012/02/26 02:29 AM
  linkMoritz2012/02/26 02:40 AM
  A bit about yourself [OT]David Kanter2012/02/27 01:40 PM
    Reply L2Moritz2012/03/01 02:20 PM
  A bit about yourself [OT]lemuel2012/05/18 02:22 PM
  A bit about yourself [OT]kk2013/06/06 02:37 PM
  A bit about yourself [OT]Oliver S.2019/08/13 12:58 AM
    A bit about yourself [OT]David Kanter2019/08/13 08:55 AM
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