Bulldozer's integer execution units

By: Exophase (exophase.delete@this.gmail.com), April 26, 2012 6:24 pm
Room: Moderated Discussions
EduardoS (no@spam.com) on 4/26/12 wrote:
---------------------------
>Ok, AGUs calculate addresses, load are listed as using EX units, the conclusion is quite obvious, don't you think?
>

Of course I think it's obvious, but there's no reasonable excuse for the SOG to omit it. The point is that it can't be a very reliable document if it omits something so fundamental.

>Not in that context, the discussion isn't exactly about how many units BD have
>but how they are arranged or how they work, and they seens to work exactly like in previous uarch.
>
>If you had read my posts you would know that I think the number of units is too
>few and isn't even theorically enough to match SB single thread IPC wich is above
>2 in many workloads, but you prefered to ignore the context and reach another conclusion.

Okay, I misunderstood your tone - I thought that you were saying that the overall execution arrangement in BD was fine as it was unchanged from K10, not merely the individual AGU/ALU pairs. I agree with your sentiments on this, although the K8 arrangement wasn't necessarily ideal (honestly I couldn't really say). Please don't take this misunderstanding to mean that I didn't read your posts or willingly ignored your point.

>
>BTW, if the AGUs were able to perform loads without the need of ALUs and also a
>few simple instructions the execution width would also be enough and Bulldozer exceed
>Greyhound in IPC, this independence of units was repeat a lto by John Fruehe and
>many others with some claiming BD could sustain four instruction per clock on a
>single thread, more and more those claimings looks like myths.
>

Agner Fog's documentation indicates that the AGUs can perform loads without issuing to the EX ports, and David said that he doesn't see why this would not be the case - can you think of anything, outside of the questionable SOG suggesting it? Have you perhaps tested it personally?

This scenario by itself is certainly not enough to exceed peak integer IPC per core ahead of K10. In theory average IPC should have increased because of better load/store re-ordering capabilities and a deeper/unified OoO window. But it's difficult to predict the impact of such a thing. Average IPC is also negatively impacted by worse cache latencies and branch mispredict penalties.

>Also the independence between ALUs and AGUs would make the forwarding network more
>complex reducing the clock speed, maybe even more complex and slower than the "oversized"
>3 ALUs + 3 AGUs in previous uarch.
>

>And finally, compared to previous uarch BD IPC only dropped a little, even increasing
>in some workloads (wich happens to be memory subsystem - are you the annoying anon
>wich require every detail explicit in every sentence? - intensive) while execution
>resources dropepd a lot and latencies increased a lot, one possible reason is a huge improvement in the memory subsytem.
>

I'd say the IPC drop was often fairly significant, but of course BD did improve other things over K10 (those I mentioned, and others like branch fusion, and if your workload supports it, FMA and XOP.. FP being a different story altogether)

No, I'm not "the annoying anon", why would I post with two different handles? I haven't really been able to determine whether or not you're including cache performance in your assessment of memory hierarchy performance (everyone else does) but if so, I can't see how you couldn't consider the small L1 and 20 cycle L2 caches to be to BD's detriment.

If you only mean the performance of main memory, the L2 and L3 latencies pile on for the main memory latency, and BD doesn't do much to improve bandwidth.

Or maybe by memory subsystem you mean the load/store units themselves? Because that is indeed where BD has improved. If this is what you mean then I think we have a communication problem.

>The only guy who did a detailed enough analyse agrees that the memory subsystem
>is fine, everyone else saw little performance difference make no effort to find
>bottlenecks and concluded that "it must be because of L2 latency since the avarage
>IPC is about one so it doesn't matter if you have two or three units"...
>
>ps: How long since I heard for the first time "avarage IPC is about"? Maybe ten years?
>

I agree that the popular argument, "average IPC is < 1 so we don't need as much execution width" is very poor. But why would the performance impact be limited to only the execution width or the memory subsystem and never both?

Do you really think that going from ~12 to ~20 cycles L2 latency while not increasing the clock speeds nearly as much carries zero penalty? And that going from 64KB L1 at 3 cycles to 16KB L1 at 4 cycles, albeit more associative, isn't going to hurt some workloads? Who is this person who did the only detailed enough analysis to lead you to this conclusion?
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                        Bulldozer's Oddities.EduardoS2012/04/23 02:15 PM
              Clustered MT as SMT for high frequencyPaul A. Clayton2012/04/20 04:10 PM
                Clustered MT as SMT for high frequencyhcl642012/04/28 12:56 AM
                  Clustered MT as SMT for high frequencyanonymous2012/04/28 01:43 AM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 02:59 PM
                      Clustered MT as SMT for high frequencyanonymous2012/04/28 08:45 PM
                  Clustered MT as SMT for high frequencyanon2012/04/28 02:13 AM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 03:23 PM
                      Clustered MT as SMT for high frequencyanon2012/04/28 06:19 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 07:58 PM
                  Clustered MT as SMT for high frequencyDavid Kanter2012/04/28 06:38 AM
                    Guessed meaning of "strong dependency model"Paul A. Clayton2012/04/28 07:24 AM
                      Guessed meaning of "strong dependency model"EduardoS2012/04/28 09:46 AM
                        *Right meaning* about "strong dependency model"hcl642012/04/28 04:59 PM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 04:24 PM
                      Clustered MT as SMT for high frequencyanonymous2012/04/28 08:50 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 09:47 PM
                          SNB widthDavid Kanter2012/04/28 09:48 PM
                            SNB widthhcl642012/04/29 02:24 AM
                      Clustered MT as SMT for high frequencyDavid Kanter2012/04/28 09:56 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 11:44 PM
                          SOI, FD vs. PDDavid Kanter2012/04/29 07:19 AM
                            SOI, FD vs. PDhcl642012/04/29 05:31 PM
                              SOI, FD vs. PDDavid Kanter2012/04/29 11:26 PM
                                SOI, FD vs. PDhcl642012/04/30 08:08 AM
                                  SOI, FD vs. PDDavid Kanter2012/04/30 09:59 AM
                                    SOI, FD vs. PDhcl642012/04/30 06:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 06:32 PM
                                        SOI, FD vs. PDhcl642012/04/30 10:47 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/01 02:24 AM
                                            SOI, FD vs. PDhcl642012/05/01 05:46 AM
                                            SOI, FD vs. PDhcl642012/05/01 06:37 AM
                                              SOI, FD vs. PDDavid Kanter2012/05/01 08:19 AM
                                          SOI, FD vs. PDhcl642012/05/01 07:39 AM
                                            PD-SOIDavid Kanter2012/05/02 12:22 PM
                                    SOI, FD vs. PDslacker2012/04/30 08:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 10:16 PM
                                        SOI, FD vs. PDslacker2012/05/01 10:04 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/02 08:19 AM
                                            SOI, FD vs. PDzou2012/05/02 12:23 PM
                  Previous discussion of clustered MTPaul A. Clayton2012/04/28 07:00 AM
                    Previous discussion of clustered MThcl642012/04/28 09:38 PM
                      Previous discussion of clustered MTDavid Kanter2012/04/30 04:37 PM
                        Previous discussion of clustered MThcl642012/04/30 07:24 PM
                          Previous discussion of clustered MTDavid Kanter2012/04/30 07:40 PM
                            Previous discussion of clustered MThcl642012/05/01 09:15 AM
                              Latency issuesDavid Kanter2012/05/02 12:01 PM
              So, what do people think of these numbers>Megol2012/04/21 01:57 AM
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