David Kanter (dkanter@realworldtech.com) on 4/25/12 wrote:
---------------------------
>Just a few quick notes from the Bulldozer ISSCC presentations:
>
>1. AGUs do INC/DEC for PUSH/POP only
>2. Single cycle data and flag bypass from any of the 4 units
>3. Replicated PRF for 8 reads and 4 writes (each unit can write 1 result)
>4. ALUs bypass to all ALUs and AGUs
>5. AGU0 bypasses to ALU0 and AGU1 to ALU1. AGUs do not bypass to each other or to the other ALU.
>6. Only ALUs produce and consume flags
>7. INC was replicated to maintain single cycle latency on certain paths
>8. The L2 cache array has a 6-cycle internal pipeline. I suspect that means the
>remaining cycles are for L1D check (4 cycles) and then 10 cycles for sending the
>request, returning the data, checking the L2 tags, etc.
>
>Hopefully this sheds a bit more light on Bulldozer.
>
>
>David
>

Actually to be very honest i do believe that the capabilities of those INT cores will remain basically the same for many more years to come BD->PD->SR->Exc->?... and its NOT important at all, if the AGLUS can crunch a little more... and even little more in the future...

I believe the Heterogeneous idea is going to catch fire (132 presentations !! )
https://amdfusion.activeevents.com/scheduler/catalog.do
and the "modular" approach of BD kind of u-arch fits hand in glove for this.

And what other better way to augment the ILP ->IPC without changing or widening the issue rate on each INT core (not a u-arch engineer that is why i ask) ?

Crazy idea: what about "macro-ops fusion", isn't possible to fuse on-the-fly 2 or more INT instructions and run them as a vector on the FPU... after all FMA is pretty common for FP, but on-the-fly... seems not a bad idea http://www.realworldtech.com/beta/forums/index.cfm?action=detail&id=62000&threadid=61766&roomid=2
.. what about for INT instructions ?

Must define a concise INT 3 operand format for x86 ?... isn't that what the extensive XOP integer pack is about ?

and it can be for more things than just add + multiply ?

only possible if by binary translation even if a native logical pack is supported ?

Register renaming for the FPU ? ... side effects ?