EduardoS (no@spam.com) on 4/20/12 wrote:
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>Joel (joel.hruska@gmail.com) on 4/20/12 wrote:
>---------------------------

>>That blows the die-size savings apart...which might still be ok, if the caches were
>>fast. They aren't. In fact, they're painfully slow. Because every L1 write is duplicated
>>in L2, L1 write latency is effectively pinned to L2 write latency.
>>
>>I still believe BD's biggest problem is its cache latencies, but the chip as it
>>shipped last year is a badly flawed piece of work.
>
>Hell... The only task Bulldozer does reasonable well is memory intensive taks,

Memory intensive is not necessarily the same as cache intensive.

>Agner have write a document saying BD memory subsystem is ok and people still point
>at it? What is needed for people to look elsewhere? Why nobody look at the 2-wide
>integer unit? The small instruction window? Always cahce latency... why not looking
>at cache bandwidth? Why not looking at anything else? Memory subsystem is ok, frankly, maybe the only part that is ok...
>
>L1 load latency is 4 cycles, like Nehalem and Sandy Bridge but BD hits a much higher
>frequency,

It hits a *slightly* higher frequency, which may be impressive if it were not 1/2 the size, 1/2 the associativity, and write-through.

> L1 store queue have 24 entries, more than enough to hide L2 20 cycles
>latency,

Write through still means it has to do the writes in the first place, so there's a power cost to it. For sustained stores, I imagine bandwidth can become limiting factor too.

> the L2 itself, at BD target frequency 20 cycles is no more latency than
>other designs with same size, all left is L3 latency, for the role it takes it is not a problem.
>

Hmm, I don't think it's all that impressive actually, if you look at other CPUs. It's perhaps not bad if you look at it by yourself, but that's the problem. You're just looking at each part in isolation. The cache and memory subsystem must be very carefully tuned to work all together.

BD has a *tiny* (by modern standards) L1 cache, and a painfully slow L2 cache. So not only do you have more L1 misses, each of them is much more costly.

POWER7 and Intel designs are going with larger L1s and far faster L2s. I think that's a much more robust approach.