EduardoS (no@spam.com) on 4/22/12 wrote:
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>anon (anon@anon.com) on 4/22/12 wrote:
>---------------------------
>>The same what? It has 2x larger caches and 2x more ways, at the same latency.
>
>Ok, see, what a big effort to not understand you are dong, eh?
>
>You question about Power7, I answear about Power7 and make a rhetorical question
>(as an attempt to make you use your brain) comparing Power7 (implicit by the context,
>it was the target of the previous question) and you compare it to Bulldozer? What's
>so difficult about text interpretation?

I did not understand any of what you wrote.

My reply you quote here was your rhetorical question about Sandy Bridge, asking why it is "not the same" as Bulldozer, or something.

>
>>No, my point is that it sucks because it has a very small (and not very fast) L1
>>cache, and a very slow L2 cache. Stop putting words into my mouth.
>
>Actually, your point is that it is different from others...

Wrong.

>
>Frankly, "small L1 and slow L2" isn't a good argument, it is incomplete,

It is not intended to be a thorough and complete analysis of exactly what BD's performance characteristics are.

You claimed BD's "memory and cache" subsystems are very good, and I pointed to one glaring example of where it is not very good.

> it doesn't
>explain why the processor would be slower than other, it doesn't include other important

It shows that L1 misses are frequent and costly.

>metrics and units and the only argument left as to why you think it is bad is because
>it is differnt from others, Greyhound had a big L1 and fast L2 and wasn't a spectacular
>CPU, in special, on benchmarks heavly dependent on mermory subsystem performance
>(I still have to use full name to you understand?) Greyhound was far away other
>CPUs, there are other metrics other than L1 size and L2 speed, there are even other
>units, you can't judge this subsystem performance based only on those two metrics!
>
>>POWER7, 8 cycle load-to-use L2 cache.
>>SB, 12 cycle load to use L2 cache.
>
>At 256kB, much simpler pipeline and memory ordering rules for Power7 and lower
>clockspeed for SB, since you will miss-understand the "clockspeed" let's say the SB have a higher stage delay.

What are you talking about? SB has lower latency per clock, and lower absolute latency of L2 cache. Yes it is smaller, of course. I'm not attempting to hide this fact!

>
>>>Of course, with only one thread Power7 and SB will have more cache avaliable but
>>>hardly the priority were single-threaded performance, they
>>
>>Yes, but that does not mean it is a good core because you can ignore the fact that single thread performance sucks.
>
>Look at your response, the processor you are talking about appeared in the sentence
>you are replying to? Your method of implicit refering to a randomly choosen object
>won't help you when talking to others, if you use the same method to read others
>comments you will likely miss-understand the entire statement.

I really don't know what you're talking about.

>
>>Your reply is full of rhetorical questions, putting words in my mouth, calling
>>me a moron, and strawman arguments. It's amazing.
>
>I call you a moron because you look like a moron, apparently you make efforts to
>not understand what you read, don't want to be called a moron? So focus your efforts
>on understanding what you are reading, if you choose random objects to fill references
>in others comments you will look as a moron, and be called such.
>

In my opinion, the problem is that you are incoherent, combative, and refuse to acknowledge my argument.

BD has a small L1 and a slow L2.