Kira (kirsc@aeterna.ru) on 4/21/12 wrote:
---------------------------
>a reader (a@b.c) on 4/21/12 wrote:
>---------------------------
>>>but the chip as it
>>>shipped last year is a badly flawed piece of work.
>>
>>that's too strong a statement.
>>
>>BD actually performs VERY well on throughput load,
>>especially when all the cores are being used.
>>
>>the problem with single-thread performance is
>>hard to pin down. maybe they need to redo some
>>key u-arch pieces. going full custom design.
>>essentially coping from Intel's playbook.
>>
>
>Two-socket Interlagos loses pretty badly to two-socket E5 on TPC-C. BD's problems
>go way beyond single-threaded performance.
>
>http://www.realworldtech.com/beta/forums/index.cfm?action=detail&id=124654&threadid=124612&roomid=2
>
>http://tpc.org/tpcc/results/tpcc_result_detail.asp?id=112041101
>>

Did i skip something ?

Actually by the 1th link you post pointing another thread here, i believe with a transposition of what is in the PDF, Xeon loses for all concerning pure performance:

Interlagos: 2.60 GHz 1,207,982 tpmC at 0.87 $/tpmC

MagnyCours : 2.2GHz 1,263,599 tpmC at 0.51 $/tpmC

Xeon (SB-E) : 3.46 GHz 1,024,380 tpmC at 0.65 $/tpmC

and the difference of clocks is significant... yes it doesn't look good for Interlagos, but looks much worst for Xeon... after all having REAL cores more than CMT and much more than SMT can count a lot in this test.