>A 6 wide issue processor for x86 is simply a pipe dream... >until there will be
>ways to considerably break the "strong dependency model" of x86 it will be out of
>reach.

What 'strong dependency model' are you talking about? That sounds like a gimmicky marketing term.

Besides, Sandy Bridge can execute 6 uops:

3 ALU, 1 LD, 1 STA, 1 STD

That's not 6 instructions, but it's 6 uops and the difference isn't that huge. In reality that could correspond to 5 instructions.

>4 may be already too much (BD is a false 4 wide issue), >since even the strongest
>Intel u-arch doesn't pass in average the 2 IPC(instructions per clock)... makes
>wonder under the law of exponential diminishing returns if even a *3 wide issue*
>like NH/SNB/IB makes sense(perhaps that is why Intel have SIMD and FP to the same ports of INt... and SMT)
>http://www.realworldtech.com/page.cfm?ArticleID=RWT091810191937&p=6

The average IPC for most code may be ~1. However, there are quite a few snippets of code where you can achieve IPC of 3 or 4. Hell, if you look at Poulson, it can issue 12 instructions/cycle. There's a reason to do that.

Peak IPC >> average IPC.

>And no NH/SNB/IB are NOT true 6 wide issue u-archs, it only >dispatches 4 uops cycle
>so 4 is the theoretical max sustainable but under certain >conditions,

SNB can sustain 5 instructions/cycle using macro-fusion.

>because it
>only has 3 uop exec ports and there are considerable >dependencies to attend(its always much much less average).
>http://www.realworldtech.com/page.cfm?ArticleID=RWT091810191937&p=5
>

Yes and there are 3 ports for memory uops.

>>As discussed here earlier, the motive seems to have been
>>to allow substantial sharing between threads in a high
>>frequency design without the data cache issues that the
>>early Pentium4 SMT suffered.
>
>As above the only things that shares threads in BD are the >FlexFPU and the L2..

And the instruction cache, fetch and decode.

>not even a remote resemblance with P4, more so because BD >pipeline length is only
>15 stages, and the first 2 or 3 stages are decoupled and >can run ahead, so like
>SNB L0, it has the propriety of pipeline stage compression, >in this case to 13 or 12.

No offense, but you clearly have no idea what you are talking about. The pipeline length for Bulldozer includes fetch, decode, issue, execute, etc.

Just because it can run ahead doesn't make the pipeline any shorter. It just hides the latency.

David