Clustered MT as SMT for high frequency

By: David Kanter (, April 28, 2012 8:56 pm
Room: Moderated Discussions
hcl64 ( on 4/28/12 wrote:
>David Kanter ( on 4/28/12 wrote:
>>>A 6 wide issue processor for x86 is simply a pipe dream... >until there will be
>>>ways to considerably break the "strong dependency model" of x86 it will be out of
>>What 'strong dependency model' are you talking about? That sounds like a gimmicky marketing term.
>>Besides, Sandy Bridge can execute 6 uops:
>>3 ALU, 1 LD, 1 STA, 1 STD
>>That's not 6 instructions, but it's 6 uops and the difference isn't that huge.
>>In reality that could correspond to 5 instructions.
>Marketing gimmicky ?...
>Strong Dependency Model, because each "block" of instructions that are dispatched
>to a scheduler must be cross-checked for dependencies *first*, and the x86 model
>assumes a very *pessimistic* relation between those instructions.. its not uncommon
>at all false dependencies when it comes to operand values >and addresses.

How is that any different from the ARM, PPC or Alpha ISAs?

>Source operand dependency prediction, alias/address and >value prediction of load operations are ways to mitigate >this.
>The "crux" is that prediction schemes can also have an >heavy tax on wasted cycles,
>complexity (can hurt clock cycle), hardware bloat (the more >precise the mechanisms
>tend to be the greater is the bloat)... and so also power.

Every other CPU has the same predictors, except for the memory order model specific things. And having a weak MOM is a pain in the ass for programmers, debuggers and pretty much everyone.

>>>4 may be already too much (BD is a false 4 wide issue), >since even the strongest
>>>Intel u-arch doesn't pass in average the 2 IPC(instructions per clock)... makes
>>>wonder under the law of exponential diminishing returns if even a *3 wide issue*
>>>like NH/SNB/IB makes sense(perhaps that is why Intel have SIMD and FP to the same ports of INt... and SMT)
>>The average IPC for most code may be ~1. However, there are quite a few snippets
>>of code where you can achieve IPC of 3 or 4. Hell, if you look at Poulson, it can
>>issue 12 instructions/cycle. There's a reason to do that.
>>Peak IPC >> average IPC.
>yes, but when the max uops that are dispatched to the schedulers(reservation station
>in Intel) are 4, guess that *peak IPC* happens much less than half the time of
>*average IPC*. If not a scheme like SMT would hardly had >any room left, don't you agree ?

The max is 4 with macro-fusion and micro-fusion, so in reality it could easily be 5. Please read my articles.

>>>And no NH/SNB/IB are NOT true 6 wide issue u-archs, it only >dispatches 4 uops cycle
>>>so 4 is the theoretical max sustainable but under certain >conditions,
>>SNB can sustain 5 instructions/cycle using macro-fusion.
>Good point, forgot about that...from the point of view of x86 not the internal
>RISC. But how effective is macro-fusion in Intel ? 1-2% of >the code ? less ? more ?

What about micro-fusion?

>>>because it
>>>only has 3 uop exec ports and there are considerable >dependencies to attend(its always much much less average).
>>Yes and there are 3 ports for memory uops.
>>>>As discussed here earlier, the motive seems to have been
>>>>to allow substantial sharing between threads in a high
>>>>frequency design without the data cache issues that the
>>>>early Pentium4 SMT suffered.
>>>As above the only things that shares threads in BD are the >FlexFPU and the L2..
>>And the instruction cache, fetch and decode.
>>>not even a remote resemblance with P4, more so because BD >pipeline length is only
>>>15 stages, and the first 2 or 3 stages are decoupled and >can run ahead, so like
>>>SNB L0, it has the propriety of pipeline stage compression, >in this case to 13 or 12.
>>No offense, but you clearly have no idea what you are talking about. The pipeline
>>length for Bulldozer includes fetch, decode, issue, execute, etc.
>>Just because it can run ahead doesn't make the pipeline any shorter. **It just hides the latency**.
>Hiding the latency was what i meant.

That's not what you said though.

>Yet the total pipeline length of BD is 15 stages without >the latency hiding effect, so hardly resembling P4.

Do you have any references for that? AMD has never publicly stated the depth, and I suspect it's much more like 20 stages.

>What resembles P4 the most, and most strikingly the Prescott variant, that everybody
>bashes as being not good and a power hog is IBM z196.

What are you talking about?

>It has proximately the same
>number of stages(more than 30), is a CISC ISA (perhaps more complex than x86), has
>complex operand forwarding networks (which can hurt clock >cycle badly) with a form of eager execution with >checkpointing

>Its a monster chip with >500mm2 with extensive RAS features(also can hurt clock
>cycle)... a power hog alright, yet its marketed at 5.2Ghz stock speed, on a 45nm
>no HKMG SOI process ... i just wonder at *IBM* 22nm FinFET >(HKMG) SOI process!.

It's amazing what you can do with a liquid cooled chip that dissipates 250W.

>Without wanting to hurt feelings, yes it seems that Intel has the best "bulk" process
>around bare none today, but perhaps the "marketing gimmicky" of the SOITEC group
>about SOI offering *up to* 40% better mobility for high >clock high performance chips, is not too much out of place.

LOL. It's off by about a factor of 5X. SOI gives at best a 7% performance advantage in 65nm and below. The benefits have consistently diminished over time.

>And if (always the *if*) Intel had gone for a SOI process back them, instead of
>exploding pipeline lengths and double pumping ALUs... >perhaps the core2 might never had happened...

If we had green eggs, we could have green eggs and ham, if we had some ham.

Intel doesn't do SOI and has very little interest except for silicon photonics.

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                        Bulldozer's Oddities.Eric2012/04/23 11:33 AM
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                            Bulldozer's Oddities.Eric2012/04/23 06:30 PM
                              Bulldozer's Oddities.hcl642012/04/27 05:16 PM
                            Bulldozer's Oddities.Y2012/04/25 03:34 AM
                              Bulldozer's IDIVHeikki Kultala2012/04/27 09:56 PM
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                        Bulldozer's Oddities.EduardoS2012/04/23 01:15 PM
              Clustered MT as SMT for high frequencyPaul A. Clayton2012/04/20 03:10 PM
                Clustered MT as SMT for high frequencyhcl642012/04/27 11:56 PM
                  Clustered MT as SMT for high frequencyanonymous2012/04/28 12:43 AM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 01:59 PM
                      Clustered MT as SMT for high frequencyanonymous2012/04/28 07:45 PM
                  Clustered MT as SMT for high frequencyanon2012/04/28 01:13 AM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 02:23 PM
                      Clustered MT as SMT for high frequencyanon2012/04/28 05:19 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 06:58 PM
                  Clustered MT as SMT for high frequencyDavid Kanter2012/04/28 05:38 AM
                    Guessed meaning of "strong dependency model"Paul A. Clayton2012/04/28 06:24 AM
                      Guessed meaning of "strong dependency model"EduardoS2012/04/28 08:46 AM
                        *Right meaning* about "strong dependency model"hcl642012/04/28 03:59 PM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 03:24 PM
                      Clustered MT as SMT for high frequencyanonymous2012/04/28 07:50 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 08:47 PM
                          SNB widthDavid Kanter2012/04/28 08:48 PM
                            SNB widthhcl642012/04/29 01:24 AM
                      Clustered MT as SMT for high frequencyDavid Kanter2012/04/28 08:56 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 10:44 PM
                          SOI, FD vs. PDDavid Kanter2012/04/29 06:19 AM
                            SOI, FD vs. PDhcl642012/04/29 04:31 PM
                              SOI, FD vs. PDDavid Kanter2012/04/29 10:26 PM
                                SOI, FD vs. PDhcl642012/04/30 07:08 AM
                                  SOI, FD vs. PDDavid Kanter2012/04/30 08:59 AM
                                    SOI, FD vs. PDhcl642012/04/30 05:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 05:32 PM
                                        SOI, FD vs. PDhcl642012/04/30 09:47 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/01 01:24 AM
                                            SOI, FD vs. PDhcl642012/05/01 04:46 AM
                                            SOI, FD vs. PDhcl642012/05/01 05:37 AM
                                              SOI, FD vs. PDDavid Kanter2012/05/01 07:19 AM
                                          SOI, FD vs. PDhcl642012/05/01 06:39 AM
                                            PD-SOIDavid Kanter2012/05/02 11:22 AM
                                    SOI, FD vs. PDslacker2012/04/30 07:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 09:16 PM
                                        SOI, FD vs. PDslacker2012/05/01 09:04 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/02 07:19 AM
                                            SOI, FD vs. PDzou2012/05/02 11:23 AM
                  Previous discussion of clustered MTPaul A. Clayton2012/04/28 06:00 AM
                    Previous discussion of clustered MThcl642012/04/28 08:38 PM
                      Previous discussion of clustered MTDavid Kanter2012/04/30 03:37 PM
                        Previous discussion of clustered MThcl642012/04/30 06:24 PM
                          Previous discussion of clustered MTDavid Kanter2012/04/30 06:40 PM
                            Previous discussion of clustered MThcl642012/05/01 08:15 AM
                              Latency issuesDavid Kanter2012/05/02 11:01 AM
              So, what do people think of these numbers>Megol2012/04/21 12:57 AM
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