>>>Without wanting to hurt feelings, yes it seems that Intel has the best "bulk" process
>>>around bare none today, but perhaps the "marketing gimmicky" of the SOITEC group
>>>about SOI offering *up to* 40% better mobility for high >clock high performance chips, is not too much out of place.
>>
>>LOL. It's off by about a factor of 5X. SOI gives at best a 7% performance advantage
>>in 65nm and below. The benefits have consistently diminished over time.
>>
>
>Marketing gimmicky perhaps !?, perhaps someone should >correct those guys, because something fishingly hot is going >on

[snip] See the difference is that those guys know what they are talking about. That's FULLY DEPLETED SOI, which is totally different from partially depleted SOI.

The term SOI means PD-SOI.

>From what i can understand from disparate sources, "planar" >bulk is DEAD after
>the 20nm processes... but the twist is that FinFET on SOI >is easier to fab,

Not really.

>provides
>better results and can even cost less, attending it can >have quite a bunch less steps(below)

Nope. You read a marketing paper from the SOI consortium how planar FD-SOI is supposedly about the same cost as bulk FinFETs.

Here's the problem, the numbers they were using were bunk. Neither Intel nor TSMC pays anything close to what was suggested for bulk wafers.

There's a reason why the two largest producers of digital logic are using FinFETS and not FD-SOI. On the other hand, much weaker and smaller players like STMicro prefer FD-SOI.

>
>Someone "close tight" to the foundry industry, not chip >marketing, is selling green eggs.. or is other way around ?

That would be the SOI Consortium...peddling rubbish since forever. Check how many people were using SOI vs. bulk.

>Really it begs the question, because if that analyses is >correct, and this news also http://www.eetimes.com/electronics-news/4371063/Silicon-on-insulator-at-ST-and-IBM-closing-gap-with-Intel

The analysis isn't correct. Also, you should note that planar FD-SOI has much worse performance than bulk FinFETs. So it's not really an option for the markets where Intel happens to be playing.

>" Intel has gone to great lengths to design FD undoped channels for its tri-gate
>FinFET transistor using standard bulk silicon wafers, which as a result *requires
>sidewall implant doping(SiO2)* to isolate the channel and >prevent excess leakage current into the substrate. "

So what?

You realize that using bulk FinFETs is probably 5-15X cheaper than FD-SOI planar?

Also, you realize that Intel is in high volume production for FinFETs...whereas nobody else is even close. You can buy a product using FinFETs - where are the FD-SOI products?

>The process of Intel is transforming a bulk substrate into >a SOI(SiO2) one under
>critical regions(not the all chip i think) of those >FinFETs...

Intel is not using SOI at all, please get your facts straight and stop spouting marketing material.

Intel is forming a fully depleted region under the gate on a bulk substrate.

SOI refers to a type of substrate, generally PD-SOI. You are talking about FD-SOI substrates.

David