SOI, FD vs. PD

By: hcl64 (mario.smarq.delete@this.gmail.com), April 29, 2012 5:31 pm
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 4/29/12 wrote:
---------------------------
>>>>Without wanting to hurt feelings, yes it seems that Intel has the best "bulk" process
>>>>around bare none today, but perhaps the "marketing gimmicky" of the SOITEC group
>>>>about SOI offering *up to* 40% better mobility for high >clock high performance chips, is not too much out of place.
>>>
>>>LOL. It's off by about a factor of 5X. SOI gives at best a 7% performance advantage
>>>in 65nm and below. The benefits have consistently diminished over time.
>>>
>>
>>Marketing gimmicky perhaps !?, perhaps someone should >correct those guys, because
>something fishingly hot is going >on
>
>[snip] See the difference is that those guys know what they are talking about.
>That's FULLY DEPLETED SOI, which is totally different from partially depleted SOI.
>
>The term SOI means PD-SOI.
>

I know perfectly the difference between Partial-Depleted and Fully-Depleted Mr. Kanter.

Actually Partial-Depleted SOI is DEAD for processes below the 32/28nm. So its even sooner than bulk. And there seems to be good competitive reasons for that(below).

ALL comparatives in the [snip] were between FD-SOI against planar bulk and FinFET bulk, and between FinFET SOI and FinFET bulk.

Which BTW if they know what they are talking about, they say FD-SOI can even be cheaper =simpler= to manufacture than planar and for sure than FinFET bulk. And last but not least provide better results(at least for sure against planar bulk), and the transition from "planar bulk" designs to "FD-SOI" designs be much simpler and so cheaper than the transition from "planar bulk" to "FinFET bulk".

>>From what i can understand from disparate sources, "planar" >bulk is DEAD after
>>the 20nm processes... but the twist is that FinFET on SOI >is easier to fab,
>
>Not really.
>

Perhaps for dirty cheap processes for things like dirty cheap chipset chips. Dirty cheap processes than doesn't matter if they are too low power, of if they provide good performance characteristics at those low power levels.That is, for dirty cheap chips that doesn't matter if they are low power enough and dirty cheap chips that doesn't matter either if the performance is high.

*The dirty cheap for the dirty cheap*. In that sense is possible that we will see *planar bulk at 14nm*. But quite frankly i doubt very much.

>>provides
>>better results and can even cost less, attending it can >have quite a bunch less steps(below)
>
>Nope. You read a marketing paper from the SOI consortium how planar FD-SOI is supposedly
>about the same cost as bulk FinFETs.
>

I thought they knew what they are talking about!

And the marketing papers don't talk how supposedly is "about the same cost". They talk about FD-SOI potentially being considerably cheaper than FinFET "bulk", and even considerably cheaper in a comparative between FinFET on SOI and FinFET on bulk for **high performance**.

http://www.eetimes.com/electronics-news/4371063/Silicon-on-insulator-at-ST-and-IBM-closing-gap-with-Intel
" Both the 2-D planar and 3-D SOI wafers cost about four-times more than bulk silicon—accounting for Intel's reluctance to use them for its tri-gate FinFET process."

Lol !... so the price seems to be a matter of volume

"Our wafers cost about $500 wafer compared to $120 for bulk silicon," said Longoria. "But their price is recouped from process simplifications to give a *three-to-10 times overall cost reduction.*"

Quite revealing(below).

>Here's the problem, the numbers they were using were bunk. Neither Intel nor TSMC
>pays anything close to what was suggested for bulk wafers.
>

bunk!!!.. i though you said "See, the difference is that those guys know what they are talking about..."

But yes, Intel and TSMC want to pay the least for the wafers, because they charge the same rates per wafer no matter if the chip performance is crap or not... not their fault, its design LOL !..

Its a sweat deal!.. and Intel is a foundry already, it has been for some time now. Actually if we account the volume of their own many chips (chipsets, processors, controllers), perhaps Intel is the biggest foundry in the world already.

>There's a reason why the two largest producers of digital logic are using FinFETS
>and not FD-SOI. On the other hand, much weaker and smaller players like STMicro prefer FD-SOI.
>

The reason is just above. Its a business, only "we" as users come to forums bickering about performance... but performance issues are mostly discarded around design not process, so the fab part is off the hook if performance is under certain envelops( the cheaper the all scale economy of fabing, the higher the profit for the foundry or fab side).

Smaller players like STMicro goes for the best because they have to have a way to differentiate, perhaps higher performance at the fab side can still have a market, not only $$ and volume. IF NOT they will be dead not too late.

IBM is kind of special, because they always charge extra-premium anyway, so their chips tend to be low to very low volume, and truly high performance in all aspects must be the differentiator factor.

>>
>>Someone "close tight" to the foundry industry, not chip >marketing, is selling green eggs.. or is other way around ?
>
>That would be the SOI Consortium...peddling rubbish since forever. Check how many people were using SOI vs. bulk.
>

As above. Its a question of volume and price. Until a breakthrough happens on SOI volume, wafers will be considerably more expensive and so adoption can remain low specially when there is a strong campaign against SOI adoption. Its a catch, the proverbial chicken & egg paradox, a catch maintained by the necessity of the big players profits, even more cause the BIG volume of chips is dirty cheap things that have litle advantage being on SOI.

But i really wonder who is peddling the most rotten rubbish.

No one wants to lose costumers, least of all the big players to smaller ones, on much better and less expensive processes, because they don't have the scale economy constraints of the big players.

No one wants to lose profit potential, so bulk remains, specially because the big players have many dirty cheap chips to make, that don't really have much advantage being on SOI, are cheap in every aspect, power performance and cost, and so by a scale economy factor all fab processes tend to gravitate around bulk.

This might yet turn into bitter words and less lawful moves ... with Intel on the market and everybody wanting to expand, soon there will be too much capacity, not constraints..

Tunning a high performance process can be quite an expense, and take considerable more time, which doesn't spell good for time-to-market marketing strategies... if it can be done on bulk, and the performance envelop accepted by the "masses", the higher (much higher) the profit for the foundry or Fab on the scale economy side.

If the performance envelop is not acceptable, too bad for the IDM, the wafer price can be renegotiated, but now its too late... and in the end the fault is from design not fab, lol... so time-to-market and volume advantages potential of bulk over SOI can also have its down sides.

That is why Nvidia is already bitching about the TSMC 20nm planar bulk process, perhaps trying to force the adoption of FinFET already at 20nm.

That is why probably the follower of AMD Vishera(for high performance enthusiast/server), will be done at IBM 22nm FinFET SOI in 2014... a transition from the now 32nm process of more than 3 years

AMD and IBM were as big on FinFET as Intel once.
http://www.physorg.com/news148751844.html

>>Really it begs the question, because if that analyses is >correct, and this news also http://www.eetimes.com/electronics-news/4371063/Silicon-on-insulator-at-ST-and-IBM-closing-gap-with-Intel
>
>The analysis isn't correct. Also, you should note that planar FD-SOI has much worse
>performance than bulk FinFETs. So it's not really an option for the markets where Intel happens to be playing.
>

Yes i can see why Intel wishes that

About performance, it depends on how good you tune for high performance... if high performance is the intended target.

FD-SOI is mostly *NOT* tunned for high performance now, it lacks good strain and stress and doping techs, that is why it can be a *lot* cheaper to fab compared to planar bulk for the same targets. This more or less depending on how crap is the crap cheap bulk process, or if they have any small pretension.

AND YES, "bulk" processes crap enough, and its quite possible it could be cheaper than FD-SOI... and not too small difference either.

Matter of fact this is the "focal point" of the all propaganda around "bulk", and the interest of foundries, the highest volume of all chips of all types, tend to gravitate to these low crap processes, because they don't have any special requirement regarding performance, sometimes not even real low power.. only price.

Matter of fact many of those are still at 65nm and 55nm, and will start to transition soon to 40nm.. the dirtiest cheap way of making bulk at 65/55/40nm.

So comparing high performance FinFET on bulk with low power FD-SOI is not oranges to oranges. Neither should it say anything about those low crap cheap bulk processes.

Yet some papers from IBM and STMicro and others suggests quite good potentiality for high performance:

Scaling
Recent Advances in FDSOI by Bruce Doris (IBM)
http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/2%20-%20Bruce%20Doris%20-%20Recent%20Advances%20in%20FDSOI.pdf

Portability
FDSOI Design Portability by Betina Hold (ARM)(yes ARM is on it)
http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/3%20-%20Betina%20Hold%20-%20FDSOI%20Design%20Portability.pdf

High Performance
FDSOI strain options FDSOI for 20nm and below by Olivier Faynot (CEA-Leti)
http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/7%20-%20Olivier%20Faynot%20-%20FDSOI%20strain%20options%20FDSOI%20for%2020nm%20and%20below.pdf

>>" Intel has gone to great lengths to design FD undoped channels for its tri-gate
>>FinFET transistor using standard bulk silicon wafers, which as a result *requires
>>sidewall implant doping(SiO2)* to isolate the channel and >prevent excess leakage current into the substrate. "
>
>So what?
>
>You realize that using bulk FinFETs is probably 5-15X cheaper than FD-SOI planar?
>

LOL, definitely a conflict here Mr. Kanter, a big hot difference... http://www.eetimes.com/electronics-news/4371063/Silicon-on-insulator-at-ST-and-IBM-closing-gap-with-Intel

"Our wafers cost about $500 wafer compared to $120 for bulk silicon," said Longoria. "But their price is recouped from process simplifications to give a **three-to-10 times overall cost reduction.**"

>Also, you realize that Intel is in high volume production for FinFETs...whereas
>nobody else is even close. You can buy a product using FinFETs - where are the FD-SOI products?
>

Very very good

ST-Ericsson's NovaThor powers smartphone
http://www.eetimes.com/electronics-news/4228137/ST-Ericsson-NovaThor-HTC-smartphone

ST-Ericsson tips Nokia Windows Phone win
http://www.eetimes.com/electronics-news/4230273/ST-Ericsson-Nokia-Windows-Phone

Yet... this from a joint-venture not well organized, in very dire straits now, and which marketing is non-existent. Did they chose FD-SOI only because of STMicro ?

Yet (also FD-SOI )
ST’s SPIRIT1 wireless transceiver cuts power budget 50% in smart meter apps
http://www.eetimes.com/electronics-products/electronic-product-reviews/sensors-transducers/4371870/ST-s-SPIRIT1-wireless-transceiver-doubles-operation-lifetime-in-smart-meter-apps

As example STMicro had last year more than the *double* of volume selling (in $$) than a big name yet small player like GloFo. Like Intel it doesn't appear on the Foundry charts because they also make their own stuff. Matter of fact AMD had almost the double the volume selling(in $$) of GloFo->they need profits-> impinge bulk.

This is what Intel wants; more for itself and less for everybody else, so SOI should NOT be a differentiator factor

Intel grabs 15% of cellular baseband market
http://www.eetimes.com/electronics-news/4371356/Intel-grabs-share-of-cellular-baseband-market

>>The process of Intel is transforming a bulk substrate into >a SOI(SiO2) one under
>>critical regions(not the all chip i think) of those >FinFETs...
>
>Intel is not using SOI at all, please get your facts straight and stop spouting marketing material.
>
>Intel is forming a fully depleted region under the gate on a bulk substrate.
>

For that *forming a fully depleted region under the gate on a bulk substrate*, its by gate wrapping around the channel, and for that the channel must be elevated from the substrate, and that is why we have what is called "fins".

But for isolation against further leakage into the substrate(a must for high performance that always have higher operating voltages) they implant a SiO2 film under the channels and gates themselves, including a side implant technique for the channel, that is, after the fins are formed, which is very hard and very expensive to do.

http://www.eetimes.com/electronics-news/4371063/Silicon-on-insulator-at-ST-and-IBM-closing-gap-with-Intel
" Intel has gone to great lengths to design FD undoped channels for its tri-gate FinFET transistor using standard bulk silicon wafers, which as a result *requires sidewall implant doping(SiO2- OXIDE ISOLATION)* to isolate the channel and prevent excess leakage current into the substrate. "

http://www.electroiq.com/articles/sst/print/volume-52/issue-11/features/Cover_Article/Comparing_SOI_and_bulk_FinFETs__Performance__manufacturing_variability__and_cost.html

***See the picture, its quite revealing***
http://www.electroiq.com/content/dam/etc/medialib/platform-7/solid-state_technology/articles/Volume_52/Issue_11/18813.res/_jcr_content/renditions/pennwell.web.500.283.gif

Putting in a broader view, a SOI wafer is already an all around implant isolated substrate... and because its uniform it can offer better results most remarkably on variability and performance, and because it doesn't require exotic techs it can be cheaper.

I don't wanted to hurt feelings, by saying that Intel FinFET is a SOI process... *No Intel doesn't use SOI wafers*... but all in all it can be a question of semantics, because in practice (THE REASON), what those exotic techs of side implant are trying to *accomplish* is the same of a SOI wafer.

>SOI refers to a type of substrate, generally PD-SOI. You are talking about FD-SOI substrates.
>
>David
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                                    SOI, FD vs. PDslacker2012/04/30 08:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 10:16 PM
                                        SOI, FD vs. PDslacker2012/05/01 10:04 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/02 08:19 AM
                                            SOI, FD vs. PDzou2012/05/02 12:23 PM
                  Previous discussion of clustered MTPaul A. Clayton2012/04/28 07:00 AM
                    Previous discussion of clustered MThcl642012/04/28 09:38 PM
                      Previous discussion of clustered MTDavid Kanter2012/04/30 04:37 PM
                        Previous discussion of clustered MThcl642012/04/30 07:24 PM
                          Previous discussion of clustered MTDavid Kanter2012/04/30 07:40 PM
                            Previous discussion of clustered MThcl642012/05/01 09:15 AM
                              Latency issuesDavid Kanter2012/05/02 12:01 PM
              So, what do people think of these numbers>Megol2012/04/21 01:57 AM
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How do you spell avocado?