SOI, FD vs. PD

By: David Kanter (, April 29, 2012 11:26 pm
Room: Moderated Discussions
First of all, I'd like to ask you to refrain from turning our forums into a giant bill board for EETimes. If you want to build link farms, do it somewhere else.

>I know perfectly the difference between Partial-Depleted >and Fully-Depleted Mr. Kanter.

Apparently, you don't.

>Actually Partial-Depleted SOI is DEAD for processes below the 32/28nm. So its even
>sooner than bulk. And there seems to be good competitive reasons for that(below).
>ALL comparatives in the [snip] were between FD-SOI against planar bulk and FinFET
>bulk, and between FinFET SOI and FinFET bulk.

Comparing FD-SOI against planar bulk is idiotic, since nobody is planning to use it in the future. The appropriate comparison is against bulk FinFETs.

>Which BTW if they know what they are talking about, they say FD-SOI can even be
>cheaper =simpler= to manufacture than planar and for sure >than FinFET bulk.

They say that...but they aren't correct. Otherwise TSMC and Intel would be using it.

>last but not least provide better results(at least for sure >against planar bulk),

Nobody cares about planar bulk. And the results are definitely inferior to FinFETs.

>and the transition from "planar bulk" designs to "FD-SOI" designs be much simpler
>and so cheaper than the transition from "planar bulk" to >"FinFET bulk".

So they say...


>>>better results and can even cost less, attending it can >have quite a bunch less steps(below)
>>Nope. You read a marketing paper from the SOI consortium how planar FD-SOI is supposedly
>>about the same cost as bulk FinFETs.
>I thought they knew what they are talking about!

That would make you foolish.

>And the marketing papers don't talk how supposedly is "about the same cost". They
>talk about FD-SOI potentially being considerably cheaper than FinFET "bulk", and
>even considerably cheaper in a comparative between FinFET >on SOI and FinFET on bulk for **high performance**.

And those claims are just as wrong and erroneous as claiming equal cost.

FD-SOI might be a tolerable solution for low volume players, targeting low performance applications. If you are doing high volume, you will use FinFETs to use less expensive substrates. If you are doing high performance, you will do FinFETs to achieve better transistor performance.

[snip crazy talk]

>>There's a reason why the two largest producers of digital logic are using FinFETS
>>and not FD-SOI. On the other hand, much weaker and smaller players like STMicro prefer FD-SOI.
>The reason is just above. Its a business, only "we" as users come to forums bickering
>about performance... but performance issues are mostly discarded around design not
>process, so the fab part is off the hook if performance is under certain envelops(
>the cheaper the all scale economy of fabing, the higher the >profit for the foundry or fab side).

No, the reason STMicro prefers FD-SOI is that they cannot afford the R&D to develop a competitive FinFET process. Moreover, they aren't really focused on high performance.

>Smaller players like STMicro goes for the best because they have to have a way
>to differentiate, perhaps higher performance at the fab side can still have a market,
>not only $$ and volume. IF NOT they will be dead not too >late.

Wrong. ST goes for FD-SOI because it lowers the capex and raises the marginal cost of production.

Intel and TSMC make totally different trade-offs because they operate at much higher volume.

>>That would be the SOI Consortium...peddling rubbish since >>forever. Check how many people were using SOI vs. bulk.
>As above. Its a question of volume and price. Until a breakthrough happens on SOI
>volume, wafers will be considerably more expensive and so adoption can remain low
>specially when there is a strong campaign against SOI >adoption.

There's no campaign against SOI. There are facts and reality.

PD-SOI is problematic for a variety of reasons:

1. High cost
2. Small performance gains (maybe 5-7%)
3. Bad for I/O (which is also true for FD-SOI)

TSMC and Intel have never used SOI. There's a reason why.

>Its a catch, the
>proverbial chicken & egg paradox, a catch maintained by the >necessity of the big
>players profits, even more cause the BIG volume of chips is >dirty cheap things that have litle advantage being on SOI.

No, the problem is that people DON'T WANT TO USE PD-SOI because it's more EXPENSIVE.

>No one wants to lose costumers, least of all the big >players to smaller ones, on
>much better and less expensive processes, because they >don't have the scale economy constraints of the big >players.

>No one wants to lose profit potential, so bulk remains, specially because the big
>players have many dirty cheap chips to make, that don't really have much advantage
>being on SOI, are cheap in every aspect, power performance and cost, and so by a
>scale economy factor all fab processes tend to gravitate >around bulk.

The only real advantages to PD-SOI are related to SERs. 5-7% performance is pretty small given the cost.

>This might yet turn into bitter words and less lawful moves ... with Intel on the
>market and everybody wanting to expand, soon there will be >too much capacity, not constraints..
>Tunning a high performance process can be quite an expense, and take considerable
>more time, which doesn't spell good for time-to-market marketing strategies... if
>it can be done on bulk, and the performance envelop ?accepted by the "masses", the
>higher (much higher) the profit for the foundry or Fab on the scale economy side.

Yeah I don't think you understand the economics. Intel and TSMC almost always prefer to make large NRE investments to lower variable cost. FinFETs are a good example of this, in comparison to FD-SOI.

FD-SOI dramatically increases variable costs.

>That is why Nvidia is already bitching about the TSMC 20nm >planar bulk process,
>perhaps trying to force the adoption of FinFET already at >20nm.

That was really just Nvidia bitching about prices.

>That is why probably the follower of AMD Vishera(for high performance enthusiast/server),
>will be done at IBM 22nm FinFET SOI in 2014... a transition >from the now 32nm process of more than 3 years

Perhaps, we'll see.

>AMD and IBM were as big on FinFET as Intel once.

Given IBM's choices concerning high-k/metal gates and PD-SOI, I am very skeptical that they have a good understanding of the economics at play. IBM doesn't do anything in high volume, and simply doesn't have the same concerns as the rest of the industry.

>>The analysis isn't correct. Also, you should note that planar FD-SOI has much worse
>>performance than bulk FinFETs. So it's not really an option for the markets where Intel happens to be playing.
>Yes i can see why Intel wishes that

It's actually not about what they wish, but reality. Every FD-SOI researcher is pretty straight forward that it's a better fit for low power and low performance than high performance.

>About performance, it depends on how good you tune for high >performance... if high performance is the intended target.

>FD-SOI is mostly *NOT* tunned for high performance now, it lacks good strain and
>stress and doping techs,

You need stress these days for performance. And the whole point of FinFETs and FD-SOI is to reduce doping!

Honestly, you really don't seem to understand what is going on.

>that is why it can be a *lot* cheaper to fab compared
>to planar bulk for the same targets. This more or less depending on how crap is
>the crap cheap bulk process, or if they have any small >pretension.

FD-SOI is more expensive than bulk. It's higher variable costs than bulk.

>>You realize that using bulk FinFETs is probably 5-15X cheaper than FD-SOI planar?
>LOL, definitely a conflict here Mr. Kanter, a big hot difference...

>"Our wafers cost about $500 wafer compared to $120 for bulk silicon," said Longoria.
>"But their price is recouped from process simplifications to give a **three-to-10 times overall cost reduction.**"

Do you think that TSMC and Intel *really* pay $120 for bulk wafers? Do you think that SOITEC is really being honest about the added costs of FinFETs?

>>Also, you realize that Intel is in high volume production for FinFETs...whereas
>>nobody else is even close. You can buy a product using FinFETs - where are the FD-SOI products?

No offense, but did you read what I wrote?

Let me be more clear.

Intel is shipping millions of bulk FinFET chips today.

NOBODY is shipping ANY FD-SOI chips, period.

STMicro has committed to using FD-SOI. They don't have products yet, and we have yet to see when they will ship.

>As example STMicro had last year more than the *double* of volume selling (in $$)
>than a big name yet small player like GloFo. Like Intel it doesn't appear on the
>Foundry charts because they also make their own stuff. >Matter of fact AMD had almost
>the double the volume selling(in $$) of GloFo->they need >profits-> impinge bulk.

Why are you even comparing semiconductor companies and foundries? That makes no sense.

Why don't you compare the revenues of ST and AMD to Intel+Nvidia+Qualcomm+TI. Oh right, and AMD is actually using quite a bit of bulk as well.

>>Intel is not using SOI at all, please get your facts straight and stop spouting marketing material.
>>Intel is forming a fully depleted region under the gate on a bulk substrate.
>For that *forming a fully depleted region under the gate on a bulk substrate*,
>its by gate wrapping around the channel, and for that the ?>channel must be elevated
>from the substrate, and that is why we have what is called >"fins".


>But for isolation against further leakage into the substrate(a must for high performance
>that always have higher operating voltages) they implant a SiO2 film under the channels
>and gates themselves, including a side implant technique for the channel, that is,
>after the fins are formed, which is very hard and very >expensive to do.

Intel indicated that the cost of FinFETs is +2-3% of the total wafer cost. They estimated that FD-SOI would cost +10%.

I've seen the "analysis" that FD-SOI is less expensive, but frankly a lot of their assumptions seem unrealistic.

More to the point, if FD-SOI is less expensive, why is TSMC doing FinFETs?

>Putting in a broader view, a SOI wafer is already an all around implant isolated
>substrate... and because its uniform it can offer better results most remarkably
>on variability and performance, and because it doesn't require exotic techs it can be cheaper.

Except it's not cheaper. It's more expensive. Ooops!

>I don't wanted to hurt feelings, by saying that Intel FinFET is a SOI process...
>*No Intel doesn't use SOI wafers*... but all in all it can be a question of semantics,
>because in practice (THE REASON), what those exotic techs of side implant are trying
>to *accomplish* is the same of a SOI wafer.

Both are fully depleted processes, but they are very different implementations. It's really not about copying FD-SOI, it's really that both techniques accomplish the same overall goal using different methods.

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                          SOI, FD vs. PDDavid Kanter2012/04/29 07:19 AM
                            SOI, FD vs. PDhcl642012/04/29 05:31 PM
                              SOI, FD vs. PDDavid Kanter2012/04/29 11:26 PM
                                SOI, FD vs. PDhcl642012/04/30 08:08 AM
                                  SOI, FD vs. PDDavid Kanter2012/04/30 09:59 AM
                                    SOI, FD vs. PDhcl642012/04/30 06:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 06:32 PM
                                        SOI, FD vs. PDhcl642012/04/30 10:47 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/01 02:24 AM
                                            SOI, FD vs. PDhcl642012/05/01 05:46 AM
                                            SOI, FD vs. PDhcl642012/05/01 06:37 AM
                                              SOI, FD vs. PDDavid Kanter2012/05/01 08:19 AM
                                          SOI, FD vs. PDhcl642012/05/01 07:39 AM
                                            PD-SOIDavid Kanter2012/05/02 12:22 PM
                                    SOI, FD vs. PDslacker2012/04/30 08:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 10:16 PM
                                        SOI, FD vs. PDslacker2012/05/01 10:04 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/02 08:19 AM
                                            SOI, FD vs. PDzou2012/05/02 12:23 PM
                  Previous discussion of clustered MTPaul A. Clayton2012/04/28 07:00 AM
                    Previous discussion of clustered MThcl642012/04/28 09:38 PM
                      Previous discussion of clustered MTDavid Kanter2012/04/30 04:37 PM
                        Previous discussion of clustered MThcl642012/04/30 07:24 PM
                          Previous discussion of clustered MTDavid Kanter2012/04/30 07:40 PM
                            Previous discussion of clustered MThcl642012/05/01 09:15 AM
                              Latency issuesDavid Kanter2012/05/02 12:01 PM
              So, what do people think of these numbers>Megol2012/04/21 01:57 AM
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