David Kanter (dkanter@realworldtech.com) on 4/30/12 wrote:
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>>FD-SOI responds strongly to back-biasing techniques (both to increase I_on, and
>>reduce I_off). As well, the effectiveness of back-biasing techniques are not diminished
>>due to scaling effects in FD-SOI. In contrast, back-biasing >on planar bulk processes
>>are not very effective at sub-100nm gate lengths.
>
>Is body biasing equally as robust for PD-SOI?

Long story short: there's no "body biasing" in regular, digital PD-SOI circuits, because the body is floating. I don't believe "back biasing" is used in PD-SOI due to the relatively thick buried oxide layer, but it might be employed for certain circuits, such as large SRAM arrays.

Unfortunately, "body biasing" and "back biasing" are frequently conflated terms. In a bulk process, they generally mean the same thing (but not if you have a triple-well process!). In an SOI process, "back biasing" literally refers to the biasing of the underlying substrate, and not the body of the transistor itself.

The terminology gets even worse. The "back bias" can be "forward biased" or "reverse biased." As a result, you will come across papers which say, "the forward back-bias..."

It's a confusing topic.