Previous discussion of clustered MT

By: David Kanter (, April 30, 2012 3:37 pm
Room: Moderated Discussions
>>Support for 6 wide execution is not so much physically
>>impractical as economically impractical. x86 is not in a
>>performance at any cost market, and most of the code run on
>>x86 is not high-ILP code.
>*I got to wonder if its necessary at all*. Perhaps heavy computational tasks can
>start to use OpenCL and heterogeneous approaches... it seams a trend, even IBM already
>has cryptographic/compression engines on die of its z196 chips, HPC is starting
>to use GPGPU pervasively... and results speak loud;

Most real HPC workloads are still using CPUs. GPUs are not nearly as efficient as vendors suggest for real algorithms that rely on substantial communication and complex data structures.

OpenCL is barely on the market, and doesn't have widespread adoption yet.

The reality is that CPU performance is still the most important factor for the vast majority of users.

Even if they don't need the performance, it still ends up as better battery life. The two are different sides of the same coin.

>MM-4172 "" Then we used OpenCL to optimize VLC’s scaling filter, which is used
>to enlarge or shrink the video on the fly during playback. This OpenCL optimization
>has achieved speedups of up to *10x* on Llano and *18x* on >Trinity compared to a competing CPU.""

Is this normally done using software or part of the dedicated video decoder? It seems like it should be part of a video decoder...

>one got to wonder about this... i bet some here use that piece of OSS (i do)...
>and when the arguing "ab noxious" is about which is 20 to 30% better, what to think
>when the arguing could be orders of magnitude... what the >future can bring. What role will be left to the CPU ?

I don't understand what you are saying. Can you try and rephrase that?

>>*It is not clear* what you mean by "strong dependency
>>model". A quick google found a use of that by you in
>>another forum where you seem to refer to memory
>>dependency checking. This is not a particularly x86
>>issue. (Yes, with only 16 GPRs x86 will have more
>>memory activity, but this is not a huge barrier and having
>>fewer GPRs helps in renaming and load-op instructions
>>communicate single-use temporaries 'registers'.)
>All over in the work of Mikko Lipasti

>>OoO can expose some ILP and wide execution can be useful
>>at times after a dependency on a long latency operation is
>>resolved (wide execution could also be helpful in branch
>>misprediction recovery with few checkpoints); but the
>>cost-benefit ratio seems to favor more moderate width.
>>>4 may be already too much (BD is a false 4 wide issue),
>>The value of 4 wide depends on design budget and design
>>goals. For Intel, high single-thread performance is more
>>practical (e.g., higher volume allowing higher absolute
>>design costs and more binning) and perhaps more important
>>than for AMD, and Intel seems committed to SMT (which
>>benefits from 'excessive' width).
>Yes OoO is here to stay, but one has to wonder what is the >future of CPU, what
>it could be like, besides being a control & access >processing element for the heterogeneous crowd.

Higher performance, lower power undoubtedly.

>In that light i don't know if a "wide" u-arch is beneficial for branch, more than
>a narrower one.

For really really branchy code, the ILP is probably minimal and a 4-wide superscalar might be limited. But a lot of code is a mix of high ILP and low ILP. For example, analytic databases typically have IPC>1. That's an important workload that is unlikely to ever migrate to GPUs.

The real point is that even if IPC = 1, you spend a lot of time waiting for memory and disk. So in reality, execution is a lot of cycles with IPC = 0 and quite a few cycles with IPC >1. You need to be able to exploit those workloads where IPC = 3, 4 or even more to keep average IPC at a reasonable level.

>Also in that light SMT can be as efficiently implemented in a narrower
>core, cause is not for heavy computations. Also if memory access will be more important
>"a run-ahead scheme", that is, continue executing speculatively based on predicted
>and stored values and addresses, after a L1 or L2 miss(cache miss mitigation), seems
>better than SMT or spMT and so efficiently done at a >narrower core also.

Run-ahead is a much simpler version of out-of-order. Judging by the results of the POWER6, it's not a particularly attractive design choice. IBM went back to OOOE pretty quickly.

>**Yes, now Intel and AMD seam to be definitely trailing different approaches:**
>Intel will try to beef even more their cores, perhaps even >more SMT ways ( 4x per
>core), complemented with good HTM support...

I'm not sure 4 threads makes sense for client systems.

>AMD seems more on a Decoupled approach (decoupled access execute) where the CPU
>will be more of a control & access processing element for their *co-processores*
>: FlexFPUs, GNC CU, CCP(cryptographic), Managed code Fabric engines(java/javascript/HSAIL/possible
>C#), DRAM I/O engines with IOMMU & DirectGMA(DMA from co-processor to co-processor)...

Honestly I don't think there's any real evidence that AMD is going that way with products. Researchers might be interested, but researchers wanted to build trace processors a decade or two ago.

Those kinds of ideas sound neat, but don't work in practice because the latency is horrific.

AMD seems to be converging around an architecture where you have a CPU and a GPU. Not sure what they are planning to do for crypto stuff...

>I'm not implying about which is better, to me none is better at all things, not
>even now... but i'm very curious about AMD approach alright, that is why i inquired
>about fusing on-the-fly 2 Integer macro-ops into one XOP >before
>really curious if even Integer processing can be done in >good extent at a co-processor
>( FlexFPU *is* a co-processor).

1. What do you mean by a coprocessor? To me the FPU is just an FPU shared by two cores. It's no more a coprocessor than the FPUs in Sandy Bridge are coprocessors.

2. Speculatively fusing x86 instructions is challenging. What if they aren't adjacent in the code stream? Macro-fusion requires this, and it's common for CMP+JMP. But that's not necessarily true for integer adds.

3. How do you handle load/store alignment?

4. How do you handle exceptions that occur between the two instructions? You'd have to do a partial register rollback.

5. How many x86 integer instructions have been extended with XOP? It's a relatively small number (add, multiply-add, compare).

Honestly, I think it would be more productive to try and speculativcely fuse FP MUL and ADD, if you had an FMA unit with intermediate rounding.

>>Width is also somewhat flexible in meaning given the
>>potential to fuse operations, and cascaded ALUs could
>>further confuse the matter.
>>BD was clearly targeting higher frequency (like P4) and
>>used a relatively small (especially for AMD) Dcache (like
>Small Dcache... i think someone already answer that, >perhaps they were too cocky
>about their pre-fetch schemes cleverness.

Well it definitely seems to have been a mistake given how slow the L2 is.

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                      In defense of Bulldozer's OdditiesDavid Kanter2012/04/28 05:29 AM
                        In defense of Bulldozer's Odditieshcl642012/04/28 01:44 PM
                          In defense of Bulldozer's OdditiesDavid Kanter2012/04/28 08:42 PM
                            In defense of Bulldozer's Odditieshcl642012/04/28 09:39 PM
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                    Bulldozer's Oddities.EduardoS2012/04/22 12:57 PM
                      Bulldozer's Oddities.mpx2012/04/23 06:04 AM
                        Bulldozer's Oddities.Eric2012/04/23 11:33 AM
                          Bulldozer's Oddities.EduardoS2012/04/23 01:22 PM
                            Bulldozer's Oddities.Eric2012/04/23 06:30 PM
                              Bulldozer's Oddities.hcl642012/04/27 05:16 PM
                            Bulldozer's Oddities.Y2012/04/25 03:34 AM
                              Bulldozer's IDIVHeikki Kultala2012/04/27 09:56 PM
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                        Bulldozer's Oddities.EduardoS2012/04/23 01:15 PM
              Clustered MT as SMT for high frequencyPaul A. Clayton2012/04/20 03:10 PM
                Clustered MT as SMT for high frequencyhcl642012/04/27 11:56 PM
                  Clustered MT as SMT for high frequencyanonymous2012/04/28 12:43 AM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 01:59 PM
                      Clustered MT as SMT for high frequencyanonymous2012/04/28 07:45 PM
                  Clustered MT as SMT for high frequencyanon2012/04/28 01:13 AM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 02:23 PM
                      Clustered MT as SMT for high frequencyanon2012/04/28 05:19 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 06:58 PM
                  Clustered MT as SMT for high frequencyDavid Kanter2012/04/28 05:38 AM
                    Guessed meaning of "strong dependency model"Paul A. Clayton2012/04/28 06:24 AM
                      Guessed meaning of "strong dependency model"EduardoS2012/04/28 08:46 AM
                        *Right meaning* about "strong dependency model"hcl642012/04/28 03:59 PM
                    Clustered MT as SMT for high frequencyhcl642012/04/28 03:24 PM
                      Clustered MT as SMT for high frequencyanonymous2012/04/28 07:50 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 08:47 PM
                          SNB widthDavid Kanter2012/04/28 08:48 PM
                            SNB widthhcl642012/04/29 01:24 AM
                      Clustered MT as SMT for high frequencyDavid Kanter2012/04/28 08:56 PM
                        Clustered MT as SMT for high frequencyhcl642012/04/28 10:44 PM
                          SOI, FD vs. PDDavid Kanter2012/04/29 06:19 AM
                            SOI, FD vs. PDhcl642012/04/29 04:31 PM
                              SOI, FD vs. PDDavid Kanter2012/04/29 10:26 PM
                                SOI, FD vs. PDhcl642012/04/30 07:08 AM
                                  SOI, FD vs. PDDavid Kanter2012/04/30 08:59 AM
                                    SOI, FD vs. PDhcl642012/04/30 05:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 05:32 PM
                                        SOI, FD vs. PDhcl642012/04/30 09:47 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/01 01:24 AM
                                            SOI, FD vs. PDhcl642012/05/01 04:46 AM
                                            SOI, FD vs. PDhcl642012/05/01 05:37 AM
                                              SOI, FD vs. PDDavid Kanter2012/05/01 07:19 AM
                                          SOI, FD vs. PDhcl642012/05/01 06:39 AM
                                            PD-SOIDavid Kanter2012/05/02 11:22 AM
                                    SOI, FD vs. PDslacker2012/04/30 07:10 PM
                                      SOI, FD vs. PDDavid Kanter2012/04/30 09:16 PM
                                        SOI, FD vs. PDslacker2012/05/01 09:04 PM
                                          SOI, FD vs. PDDavid Kanter2012/05/02 07:19 AM
                                            SOI, FD vs. PDzou2012/05/02 11:23 AM
                  Previous discussion of clustered MTPaul A. Clayton2012/04/28 06:00 AM
                    Previous discussion of clustered MThcl642012/04/28 08:38 PM
                      Previous discussion of clustered MTDavid Kanter2012/04/30 03:37 PM
                        Previous discussion of clustered MThcl642012/04/30 06:24 PM
                          Previous discussion of clustered MTDavid Kanter2012/04/30 06:40 PM
                            Previous discussion of clustered MThcl642012/05/01 08:15 AM
                              Latency issuesDavid Kanter2012/05/02 11:01 AM
              So, what do people think of these numbers>Megol2012/04/21 12:57 AM
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