aaron spink (aaronspink.delete@this.notearthlink.net) on July 29, 2012 5:39 am wrote:
> Also lets not forget that by the time this
> happens we are likely going to see some form of stacked memory in reasonably
> wide use, which means that the CPUs will likely have 1-4 GB of ultra high
> bandwidth "cache". Which if used right would provide enough bandwidth buffer to
> have the I/Os plus having the option to direct route to/from networkMIC would
> make the 102.4 GB/s CPU memory subsystem reasonable.
>

Would it be possible to have separate memory controllers (presumably there could be several controllers to provide a very wide bus, like on a GPU) for the stacked memory and map parts of the coherent (CPU) memory space to that DRAM? I.e. some range of the memory addresses could refer to those memory controllers and offer extreme bandwidth (but limited capacity) for vector processing. I'm not exactly sure how that would be handled by software and programmers, if the hardware part is viable, but with proper OS support I'm guessing that segments of the virtual memory space could be reserved for the physical memory addresses mapped to the stacked memory. As far as I can figure that solution would be compatible with both integrated LRB cores in the CPU uncore (as has been speculated to appear in Skylake) or with AVX execution units in the core.