EduardoS (no.delete@this.spam.com) on August 7, 2012 1:54 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on August 7, 2012 1:34 am
> wrote:
> > SPARC-T4
> > derivative with 1.5x single thread performance of
> Sparc64 VII+?
> > Indeed, Sparc64
> > VII+ single-thread performance sucks,
> but does it suck THAT much?
>
> UltraSPARC T4 is a OoO processor with a few very
> strong points in single-thread performance like the load/store unit, if
> "derivate" means giving T4 single-thread more resources to play with it won't be
> difficult for this chip to beat Sparc64 VII+, specially in the memory-intensive
> targeted workload.

Still, isn't SPARC T4 a 2-way superscalar with very long integer pipeline, small L1 caches (L1D write through? I can't find info about that), very small private L2 cache and small shared L3 cache?
Yes, for throughput SPARC T4 3-level cache hierarchy is immensely better than 2-level hierarchy of Sparc64, but for single-thread performance relatively low L2 throughput of Sparc64 is not so critical. On the other hand, for the single-thread (and for scalability to high number of sockets, but that's off topic) you want as big LLC as you can afford and that's where Sparc64 is miles ahead.

So, narrower than Sparc64, longer pipeline, throughput-oriented cache hierarchy... And suspicious absence of SpecInt submissions.