Michael S (already5chosen.delete@this.yahoo.com) on August 7, 2012 3:24 am wrote:
> Still, isn't SPARC T4 a 2-way superscalar with very long
> integer pipeline, small L1 caches (L1D write through? I can't find info about
> that), very small private L2 cache and small shared L3 cache?
> Yes, for
> throughput SPARC T4 3-level cache hierarchy is immensely better than 2-level
> hierarchy of Sparc64, but for single-thread performance relatively low L2
> throughput of Sparc64 is not so critical. On the other hand, for the
> single-thread (and for scalability to high number of sockets, but that's off
> topic) you want as big LLC as you can afford and that's where Sparc64 is miles
> ahead.
>
> So, narrower than Sparc64, longer pipeline, throughput-oriented cache
> hierarchy... And suspicious absence of SpecInt submissions.

Who is saying M4 is the same chip as T4? Maybe based on T4 but not the same chip, the convergence is on the roadmap for the future.

Not being the same chip means it could have a different cache hierarchy as well as > 2-way.