Richard Cownie (tich.delete@this.pobox.com) on August 14, 2012 3:57 am wrote:
> anon (anon.delete@this.anon.com) on August 14, 2012 2:37 am wrote:
> > David
> Kanter (dkanter.delete@this.realworldtech.com) on August 14, 2012 12:04 am
> >
> wrote:
> > > The new ARMv8 architecture is classically British; a clean and
>
> > elegant 64-bit
>
> I makes me a little sad - the delightful quirks of the
> original ARM are going
> (predication, LDM/STM, a free shift on every ALU op, FIQ
> registers) - in favor of
> a more generic vanilla RISC. But I look forward to
> seeing how fast they can make
> it go.

I think it's a confirmation that RISC is still useful, and that ease of decode and execution is at least as important as instruction footprint size.

Speaking of which (and wildly changing topic), I do wonder why IBM has virtually ignored this segment of the market (from smartphones to tablets to energy efficient servers). There are ISAs entrenched already, but that hasn't stopped Intel and ARM trying to break into respective hostile markets. Quite odd, considering where else they have pushed powerpc.

>
> The support for 64KB pages looks
> interesting, that seems potentially more useful
> than x86's 4MB huge pages, and
> probably a good fit for today's big DRAM sizes
> and big-block paging
> devices.

I was sad to see when powerpc implemented 64K pages actually, and am equally sad for ARM64. I think 16K would be a good modern tradeoff. But 64K is almost unusable for many desktop/workstation/small server uses in Linux. And if you have a JVM or DBMS or hypervisor which wants to allocate huge chunks and do its own memory management, then megabyte sized pages is what you want. 64K is just an awkward size.

But better than nothing, certainly.

>
> > Do you know if
> > implementations are going to execute 32
> bit ARMv7 code at full speed? In that
> > case, won't predication shifting
> and addressing etc still complicate execution?
> > What's the plan
> there?
>
> I expect, as usual with ARM, the plan is for various teams to design
> it whichever
> way fits their product: so we'll probably see 32/64-compatible
> reference designs
> from ARM plc, but also some different cores from Qualcomm,
> Apple etc with different
> tradeoffs. I guess one way to go would be to run the
> 32bit mode, but slowly, with
> an extra cycle for the difficult
> instructions.

Yes, I would imagine, at least for most devices from ARM, difficult instructions will be slowly relegated to being cracked into multiple ops or even microcode.