anon (anon.delete@this.anon.com) on August 14, 2012 5:28 am wrote:
> none (none.delete@this.none.com) on August 14, 2012 4:44 am wrote:
> > Richard
> Cownie (tich.delete@this.pobox.com) on August 14, 2012 3:57 am
> >
> wrote:
> > > anon (anon.delete@this.anon.com) on August 14, 2012 2:37 am
>
> > wrote:
> > > > David
> > > Kanter
> (dkanter.delete@this.realworldtech.com) on
> > August 14, 2012 12:04 am
> >
> > >
> > > wrote:
> > > > > The new ARMv8
> >
> architecture is classically British; a clean and
> > >
> > > >
> elegant
> > 64-bit
> > >
> > > I makes me a little sad - the
> delightful quirks of
> > the
> > > original ARM are going
> > >
> (predication, LDM/STM, a free shift on
> > every ALU op, FIQ
> > >
> registers) - in favor of
> > > a more generic vanilla
> > RISC. But I
> look forward to
> > > seeing how fast they can make
> > > it
> >
> go.
> >
> > Some data processing instructions still have the shift
> capability:
> > add/sub, logical. You should take a look at the binutils
> patch that was posted
> > a few days ago :-)
> >
> > IMHO predication is
> not worth the trouble. With advanced
> > micro architectures, you'd better
> implement a good branch predictor rather than
> > spending time implementing
> predication (which cost can be high).
>
> What makes you say that?
>
> Intel and
> AMD both spend effort to make cmov for example run fast and low latency. Intel
> optimization manual recommends using it. Eliminating fundamentally unpredictable
> branches will reduce pressure on branch predictor for predictable branches and
> avoid mispredicts.

(For very short sequences, I should add, and particularly where your branch halves are much shorter than mispredict pipeline and you don't add extra cache references. max(a, b) would be a prime example.)