Kenneth Jonsson (kj.delete@this.localhost.org) on August 16, 2012 2:35 pm wrote:
> I have never developed a compiler, but looking at code generated by GCC for ARM,
> x86_64, MIPS and PPC begs the question: is there really any real benefit in
> having more than 16 GPRs? I cannot really see that the 16GPRs that ARM and
> x86_64 has is a limitation in close to 100% of the functions, a large number of
> the functions uses less than 8 registers. This is also true on PPC and MIPS
> where 32 GPRs are available, most register seem to just sit there
> unused.
>
> More register does increase the cost of switching context, so unused
> register cannot be a good thing.

A context switch is a simple read/write from a linear
region.

What makes them expensive is all the lost state for
prefetching, predicting and the page tables.

The decision to use 32 64bit registers is pragmatic, but I
don't think it is good reasoning:

Warning: the following is all assumption

ARM wants to use OoO, thus they have to treat banked
registers the same as normal registers and let them use
the same set of shadow registers, otherwise the micro-
architecture won't be efficient.

In 64bit mode there are no banked registers. But they still
use shadow registers if at any point in time any 32bit
legacy code ran.

If there was no access to the banked registers as normal
registers in 64bit mode, they would be lost outside 32bit
mode.

64bit mode needs more/bigger registers anyway (they
implement a 64bit register as 2x32bit registers if I
interpret the ISA correctly), so losing shadow registers
would hurt performance.

ARM needs to make sure the banked registers don't waste
important resources and the easiest way is to give them to
the programmer as normal registers.

And because they want to make it easy to program 32bit mode
from 64bit mode, they give these former shadowed registers
R16-R31.

And this is were legacy support bites them. 32 registers
aren't necessary. 16-24 could be good enough, with the
other 8 reserved for special encodings. But because it works
so well with the microarchitecture and allows legacy support
they do it.

ARM isn't x86, and 64bit could have given them a clean
break with the legacy interrupt mechanism, which isn't
usable for embedded code anyway which wants 64bit mode and
fast interrupts at the same time.

But the virtualisation 4x2 matrix is as much of a nightmare,
so I'm assuming it's just bad decisions everywhere.

*otherwise they all could point to an imaginary 0 register.