Article: ARM Goes 64-bit
By: Kenneth Jonsson (kj.delete@this.localhost.org), August 17, 2012 10:54 am
Room: Moderated Discussions
Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on August 17, 2012 6:31 am wrote:
>
> These results are
> wrong - it is trivial to write a function which uses all registers, so pretty
> much impossible they are unused in ~70k instructions. Did you compile with all
> optimizations disabled or perhaps used an old disassembler? (sl,fp,ip were used
> for r10-r12 in the past). Btw you need to include SP and LR as both are GPRs
> (with some special purpose instructions).
>
> Wilco
I compiled with -O2 (recompiled now and double-checked that -O2 and no -O0 was passed to the compiler) and I excluded r13 (stack pointer, which "objdump" show as "sp"), r14 (link register, shown as "lr") and r15 (program counter, listed as "pc"). The compiler is gcc 4.3.3, so not the latest and greatest. I got all this information via objdump, sed, sort and uniq and I'm not a expert on sed. But I opened the full output from "objdump -d" in emacs to double-check that those registers weren't use, only thing I saw with "r11" in was "cr11".
Also, I think my sed reg-exp is correct as they managed to extract the PPC registers r10-r31.
What I did was dumping the whole image file as assembler code, cut out all characters up to the opcode, located every match for r[0-9]+, put the match on a separate line and deleted everything else, i.e.
101e8: e0000492 mul r0, r2, r4
would become
r0
r2
r4
after my "sed" step
Sorted that output, sent it to "uniq -c". I'm not saying that this method is fool-proof or even 100% correct, but it seems to be close enough to get the general trend. And that seem to be that there are very few occasions where 16 or even 8 GPRs seem to be a limiting factor for a modern compiler.
But you are right, it is very odd that three registers would not be used at all, especially as PPC and MIPS used all registers even if quite a lot of them was used quite rarely.
BTW, I tried the same thing on x86_64 using ICC and GCC on a slightly bigger image that contain all the things the ARM version contained + some more stuff. I just post the RAW figures, first column is the number of times the register was used, second column the name (as presented by objdump)
ICC seem to have more spread of its use of registers, but both compilers hardly uses r10 and r11. ICC does generate more instructions tough...
ICC, 550k instructions using at least one of the registers below
20 %xmm11
30 %xmm9
33 %xmm8
47 %r11w
49 %r15w
51 %r11b
55 %r13w
61 %r10w
62 %r9w
64 %r14w
65 %ebp
71 %di
77 %r10b
83 %r12w
83 %r9b
85 %xmm6
88 %xmm10
89 %xmm7
90 %xmm5
91 %r14b
114 %r13b
116 %bx
118 %xmm4
121 %r8w
123 %si
132 %r12b
137 %xmm3
168 %esp
172 %sil
235 %cx
235 %r8b
246 %cs
317 %xmm2
370 %ch
409 %xmm1
431 %dh
536 %bl
676 %dx
688 %bh
749 %xmm0
793 %dil
820 %r15b
849 %ah
1325 %dl
1557 %r11d
1759 %r11
1849 %r10d
2497 %r10
2763 %r9
3159 %r9d
3298 %ax
3900 %r15d
4082 %r14d
4543 %r8
4648 %r13d
4735 %r8d
5724 %r12d
8567 %ebx
10045 %cl
10398 %rip
11137 %edi
13496 %ecx
13505 %esi
14344 %r15
16712 %r14
20295 %r13
20479 %rcx
20579 %edx
21177 %rsp
21901 %rdx
23871 %r12
29124 %rsi
35488 %rbx
36093 %rdi
55063 %al
60391 %eax
69022 %rbp
102955 %rax
GCC, 470k instructions using at least one of the registers below
2 %bpl
2 %xmm15
3 %spl
4 %r11w
6 %xmm12
9 %r10w
10 %r9w
20 %r11b
20 %xmm11
23 %r15w
30 %xmm9
35 %xmm8
37 %r10b
41 %r9b
46 %di
46 %r8w
48 %r13w
57 %r14w
58 %r12w
71 %bx
86 %xmm6
88 %xmm10
89 %xmm7
90 %xmm5
94 %r14b
108 %si
118 %xmm4
131 %cx
131 %ebp
133 %r13b
137 %xmm3
141 %sil
152 %r12b
170 %r8b
317 %xmm2
370 %esp
409 %xmm1
606 %dh
728 %ch
752 %r10d
753 %xmm0
800 %r11d
808 %bl
817 %dx
1002 %r15b
1129 %r10
1134 %cl
1229 %dil
1507 %ah
1598 %r15d
1653 %dl
1768 %r9
1768 %r9d
1962 %r11
1999 %bh
2219 %es
2452 %r14d
2794 %r8
3015 %r8d
3253 %r13d
4517 %r12d
4625 %ax
6272 %r15
7636 %ebx
7732 %ecx
8804 %r14
8896 %edi
9267 %rip
10833 %esi
13820 %r13
14573 %rcx
16122 %edx
17633 %rsp
19526 %rdx
20600 %r12
22977 %rsi
30565 %rdi
34351 %rbx
42926 %rbp
46055 %al
50594 %eax
101687 %rax
>
> These results are
> wrong - it is trivial to write a function which uses all registers, so pretty
> much impossible they are unused in ~70k instructions. Did you compile with all
> optimizations disabled or perhaps used an old disassembler? (sl,fp,ip were used
> for r10-r12 in the past). Btw you need to include SP and LR as both are GPRs
> (with some special purpose instructions).
>
> Wilco
I compiled with -O2 (recompiled now and double-checked that -O2 and no -O0 was passed to the compiler) and I excluded r13 (stack pointer, which "objdump" show as "sp"), r14 (link register, shown as "lr") and r15 (program counter, listed as "pc"). The compiler is gcc 4.3.3, so not the latest and greatest. I got all this information via objdump, sed, sort and uniq and I'm not a expert on sed. But I opened the full output from "objdump -d" in emacs to double-check that those registers weren't use, only thing I saw with "r11" in was "cr11".
Also, I think my sed reg-exp is correct as they managed to extract the PPC registers r10-r31.
What I did was dumping the whole image file as assembler code, cut out all characters up to the opcode, located every match for r[0-9]+, put the match on a separate line and deleted everything else, i.e.
101e8: e0000492 mul r0, r2, r4
would become
r0
r2
r4
after my "sed" step
Sorted that output, sent it to "uniq -c". I'm not saying that this method is fool-proof or even 100% correct, but it seems to be close enough to get the general trend. And that seem to be that there are very few occasions where 16 or even 8 GPRs seem to be a limiting factor for a modern compiler.
But you are right, it is very odd that three registers would not be used at all, especially as PPC and MIPS used all registers even if quite a lot of them was used quite rarely.
BTW, I tried the same thing on x86_64 using ICC and GCC on a slightly bigger image that contain all the things the ARM version contained + some more stuff. I just post the RAW figures, first column is the number of times the register was used, second column the name (as presented by objdump)
ICC seem to have more spread of its use of registers, but both compilers hardly uses r10 and r11. ICC does generate more instructions tough...
ICC, 550k instructions using at least one of the registers below
20 %xmm11
30 %xmm9
33 %xmm8
47 %r11w
49 %r15w
51 %r11b
55 %r13w
61 %r10w
62 %r9w
64 %r14w
65 %ebp
71 %di
77 %r10b
83 %r12w
83 %r9b
85 %xmm6
88 %xmm10
89 %xmm7
90 %xmm5
91 %r14b
114 %r13b
116 %bx
118 %xmm4
121 %r8w
123 %si
132 %r12b
137 %xmm3
168 %esp
172 %sil
235 %cx
235 %r8b
246 %cs
317 %xmm2
370 %ch
409 %xmm1
431 %dh
536 %bl
676 %dx
688 %bh
749 %xmm0
793 %dil
820 %r15b
849 %ah
1325 %dl
1557 %r11d
1759 %r11
1849 %r10d
2497 %r10
2763 %r9
3159 %r9d
3298 %ax
3900 %r15d
4082 %r14d
4543 %r8
4648 %r13d
4735 %r8d
5724 %r12d
8567 %ebx
10045 %cl
10398 %rip
11137 %edi
13496 %ecx
13505 %esi
14344 %r15
16712 %r14
20295 %r13
20479 %rcx
20579 %edx
21177 %rsp
21901 %rdx
23871 %r12
29124 %rsi
35488 %rbx
36093 %rdi
55063 %al
60391 %eax
69022 %rbp
102955 %rax
GCC, 470k instructions using at least one of the registers below
2 %bpl
2 %xmm15
3 %spl
4 %r11w
6 %xmm12
9 %r10w
10 %r9w
20 %r11b
20 %xmm11
23 %r15w
30 %xmm9
35 %xmm8
37 %r10b
41 %r9b
46 %di
46 %r8w
48 %r13w
57 %r14w
58 %r12w
71 %bx
86 %xmm6
88 %xmm10
89 %xmm7
90 %xmm5
94 %r14b
108 %si
118 %xmm4
131 %cx
131 %ebp
133 %r13b
137 %xmm3
141 %sil
152 %r12b
170 %r8b
317 %xmm2
370 %esp
409 %xmm1
606 %dh
728 %ch
752 %r10d
753 %xmm0
800 %r11d
808 %bl
817 %dx
1002 %r15b
1129 %r10
1134 %cl
1229 %dil
1507 %ah
1598 %r15d
1653 %dl
1768 %r9
1768 %r9d
1962 %r11
1999 %bh
2219 %es
2452 %r14d
2794 %r8
3015 %r8d
3253 %r13d
4517 %r12d
4625 %ax
6272 %r15
7636 %ebx
7732 %ecx
8804 %r14
8896 %edi
9267 %rip
10833 %esi
13820 %r13
14573 %rcx
16122 %edx
17633 %rsp
19526 %rdx
20600 %r12
22977 %rsi
30565 %rdi
34351 %rbx
42926 %rbp
46055 %al
50594 %eax
101687 %rax
Topic | Posted By | Date |
---|---|---|
New Article: ARM Goes 64-bit | David Kanter | 2012/08/13 11:04 PM |
New Article: ARM Goes 64-bit | none | 2012/08/13 11:44 PM |
New Article: ARM Goes 64-bit | David Kanter | 2012/08/14 12:04 AM |
MIPS MT-ASE | Paul A. Clayton | 2012/08/14 08:01 AM |
MONITOR/MWAIT | EduardoS | 2012/08/14 09:08 AM |
MWAIT not specifically MT | Paul A. Clayton | 2012/08/14 09:36 AM |
MWAIT not specifically MT | EduardoS | 2012/08/15 02:16 PM |
MONITOR/MWAIT | anonymou5 | 2012/08/14 10:07 AM |
MONITOR/MWAIT | EduardoS | 2012/08/15 02:20 PM |
MIPS MT-ASE | rwessel | 2012/08/14 09:14 AM |
New Article: ARM Goes 64-bit | SHK | 2012/08/14 01:01 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 01:37 AM |
New Article: ARM Goes 64-bit | Richard Cownie | 2012/08/14 02:57 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 03:29 AM |
New Article: ARM Goes 64-bit | none | 2012/08/14 03:44 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 04:28 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 04:32 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/08/14 05:06 AM |
New Article: ARM Goes 64-bit | none | 2012/08/14 04:40 AM |
AArch64 select better than cmov | Paul A. Clayton | 2012/08/14 05:08 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 05:12 AM |
New Article: ARM Goes 64-bit | none | 2012/08/14 05:25 AM |
Predicated ld/store are useful | Paul A. Clayton | 2012/08/14 05:48 AM |
Predicated ld/store are useful | none | 2012/08/14 05:56 AM |
Predicated ld/store are useful | anon | 2012/08/14 06:07 AM |
Predicated stores might not be that bad | Paul A. Clayton | 2012/08/14 06:27 AM |
Predicated stores might not be that bad | David Kanter | 2012/08/15 12:14 AM |
Predicated stores might not be that bad | Michael S | 2012/08/15 10:41 AM |
Predicated stores might not be that bad | R Byron | 2012/08/17 03:09 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 05:54 AM |
New Article: ARM Goes 64-bit | none | 2012/08/14 06:04 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 06:43 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/08/14 05:07 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 05:20 AM |
New Article: ARM Goes 64-bit | none | 2012/08/14 05:29 AM |
New Article: ARM Goes 64-bit | anon | 2012/08/14 06:00 AM |
New Article: ARM Goes 64-bit | Michael S | 2012/08/14 02:43 PM |
New Article: ARM Goes 64-bit | Richard Cownie | 2012/08/14 05:53 AM |
OT: Conrad's "Youth" | Richard Cownie | 2012/08/14 06:20 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/08/14 05:04 AM |
New Article: ARM Goes 64-bit | mpx | 2012/08/14 07:59 AM |
New Article: ARM Goes 64-bit | Antti-Ville Tuunainen | 2012/08/14 08:16 AM |
New Article: ARM Goes 64-bit | anonymou5 | 2012/08/14 10:03 AM |
New Article: ARM Goes 64-bit | name99 | 2012/11/17 02:31 PM |
Microarchitecting a counter register | Paul A. Clayton | 2012/11/17 06:37 PM |
New Article: ARM Goes 64-bit | bakaneko | 2012/08/14 03:21 AM |
New Article: ARM Goes 64-bit | name99 | 2012/11/17 02:40 PM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/17 03:52 PM |
New Article: ARM Goes 64-bit | Doug S | 2012/11/17 04:48 PM |
New Article: ARM Goes 64-bit | bakaneko | 2012/11/18 04:40 PM |
New Article: ARM Goes 64-bit | Wilco | 2012/11/19 06:59 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/19 07:23 AM |
New Article: ARM Goes 64-bit | Wilco | 2012/11/19 08:31 AM |
Downloading µarch-specific binaries? | Paul A. Clayton | 2012/11/19 10:21 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/19 10:41 AM |
New Article: ARM Goes 64-bit | Wilco | 2012/11/21 06:44 AM |
JIT vs. static compilation (Was: New Article: ARM Goes 64-bit) | VMguy | 2012/11/22 02:21 AM |
JIT vs. static compilation (Was: New Article: ARM Goes 64-bit) | David Kanter | 2012/11/22 11:12 AM |
JIT vs. static compilation (Was: New Article: ARM Goes 64-bit) | Gabriele Svelto | 2012/11/23 02:50 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/23 09:09 AM |
New Article: ARM Goes 64-bit | EBFE | 2012/11/26 12:24 AM |
New Article: ARM Goes 64-bit | Gabriele Svelto | 2012/11/26 02:33 AM |
New Article: ARM Goes 64-bit | EBFE | 2012/11/27 10:17 PM |
New Article: ARM Goes 64-bit | Gabriele Svelto | 2012/11/28 01:32 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/26 11:16 AM |
New Article: ARM Goes 64-bit | EBFE | 2012/11/27 11:33 PM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/28 04:53 AM |
New Article: ARM Goes 64-bit | Michael S | 2012/11/28 05:15 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/28 06:33 AM |
New Article: ARM Goes 64-bit | Michael S | 2012/11/28 08:16 AM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/28 08:53 AM |
New Article: ARM Goes 64-bit | Eugene Nalimov | 2012/11/28 04:58 PM |
Amazing! | EduardoS | 2012/11/28 06:25 PM |
Amazing! (non-italic response) | EduardoS | 2012/11/28 06:25 PM |
Amazing! | EBFE | 2012/11/28 07:20 PM |
Undefined behaviour doubles down | EduardoS | 2012/11/28 08:10 PM |
New Article: ARM Goes 64-bit | EBFE | 2012/11/28 06:54 PM |
New Article: ARM Goes 64-bit | EduardoS | 2012/11/28 08:21 PM |
Have you heard of Transmeta? | David Kanter | 2012/11/19 02:47 PM |
New Article: ARM Goes 64-bit | bakaneko | 2012/11/19 08:08 AM |
New Article: ARM Goes 64-bit | David Kanter | 2012/11/19 02:40 PM |
Semantic Dictionary Encoding | Ray | 2012/11/19 09:37 PM |
New Article: ARM Goes 64-bit | Rohit | 2012/11/20 03:48 PM |
New Article: ARM Goes 64-bit | David Kanter | 2012/11/20 10:07 PM |
New Article: ARM Goes 64-bit | Wilco | 2012/11/21 05:41 AM |
New Article: ARM Goes 64-bit | David Kanter | 2012/11/21 09:12 AM |
A JIT example | Mark Roulo | 2012/11/21 09:30 AM |
A JIT example | Wilco | 2012/11/21 06:04 PM |
A JIT example | rwessel | 2012/11/21 08:05 PM |
A JIT example | Gabriele Svelto | 2012/11/23 02:53 AM |
A JIT example | EduardoS | 2012/11/23 09:13 AM |
A JIT example | Wilco | 2012/11/23 12:41 PM |
A JIT example | EduardoS | 2012/11/23 01:06 PM |
A JIT example | Gabriele Svelto | 2012/11/23 03:09 PM |
A JIT example | Symmetry | 2012/11/26 04:58 AM |
New Article: ARM Goes 64-bit | Ray | 2012/11/19 09:27 PM |
New Article: ARM Goes 64-bit | David Kanter | 2012/08/14 08:11 AM |
v7-M is Thumb-only | Paul A. Clayton | 2012/08/14 05:58 AM |
Minor suggested correction | Paul A. Clayton | 2012/08/14 07:33 AM |
Minor suggested correction | anon | 2012/08/14 07:57 AM |
New Article: ARM Goes 64-bit | Exophase | 2012/08/14 07:33 AM |
New Article: ARM Goes 64-bit | David Kanter | 2012/08/14 08:16 AM |
New Article: ARM Goes 64-bit | jigal | 2012/08/15 12:49 PM |
Correction re ARM and BBC Micro | Paul | 2012/08/14 07:59 PM |
Correction re ARM and BBC Micro | Per Hesselgren | 2012/08/15 02:27 AM |
Memory BW so low | Per Hesselgren | 2012/08/15 02:14 AM |
Memory BW so low | none | 2012/08/15 10:16 AM |
New Article: ARM Goes 64-bit | dado | 2012/08/15 09:25 AM |
Number of GPRs | Kenneth Jonsson | 2012/08/16 01:35 PM |
Number of GPRs | Exophase | 2012/08/16 01:52 PM |
Number of GPRs | Kenneth Jonsson | 2012/08/17 01:41 AM |
Ooops, missing link... | Kenneth Jonsson | 2012/08/17 01:44 AM |
64-bit pointers eat some performance | Paul A. Clayton | 2012/08/17 05:19 AM |
64-bit pointers eat some performance | bakaneko | 2012/08/17 07:37 AM |
Brute force seems to work | Paul A. Clayton | 2012/08/17 09:08 AM |
Brute force seems to work | bakaneko | 2012/08/17 10:15 AM |
64-bit pointers eat some performance | Richard Cownie | 2012/08/17 07:46 AM |
Pointer compression is atypical | Paul A. Clayton | 2012/08/17 09:43 AM |
Pointer compression is atypical | Richard Cownie | 2012/08/17 11:57 AM |
Pointer compression is atypical | Howard Chu | 2012/08/22 09:17 PM |
Pointer compression is atypical | Richard Cownie | 2012/08/23 03:48 AM |
Pointer compression is atypical | Howard Chu | 2012/08/23 05:51 AM |
Pointer compression is atypical | Wilco | 2012/08/17 01:41 PM |
Pointer compression is atypical | Richard Cownie | 2012/08/17 03:13 PM |
Pointer compression is atypical | Ricardo B | 2012/08/19 09:44 AM |
Pointer compression is atypical | Howard Chu | 2012/08/22 09:08 PM |
Unified libraries? | Paul A. Clayton | 2012/08/23 06:49 AM |
Pointer compression is atypical | Richard Cownie | 2012/08/23 07:44 AM |
Pointer compression is atypical | Howard Chu | 2012/08/23 04:17 PM |
Pointer compression is atypical | anon | 2012/08/23 07:15 PM |
Pointer compression is atypical | Howard Chu | 2012/08/23 08:33 PM |
64-bit pointers eat some performance | Foo_ | 2012/08/18 11:09 AM |
64-bit pointers eat some performance | Richard Cownie | 2012/08/18 04:25 PM |
64-bit pointers eat some performance | Richard Cownie | 2012/08/18 04:32 PM |
Page-related benefit of small pointers | Paul A. Clayton | 2012/08/23 07:36 AM |
Number of GPRs | Wilco | 2012/08/17 05:31 AM |
Number of GPRs | Kenneth Jonsson | 2012/08/17 10:54 AM |
Number of GPRs | Exophase | 2012/08/17 11:44 AM |
Number of GPRs | Kenneth Jonsson | 2012/08/17 12:22 PM |
Number of GPRs | Wilco | 2012/08/17 01:53 PM |
What about dynamic utilization? | Exophase | 2012/08/17 08:30 AM |
Compiler vs. assembly aliasing knowledge? | Paul A. Clayton | 2012/08/17 09:20 AM |
Compiler vs. assembly aliasing knowledge? | Exophase | 2012/08/17 10:09 AM |
Compiler vs. assembly aliasing knowledge? | anon | 2012/08/18 01:23 AM |
Compiler vs. assembly aliasing knowledge? | Ricardo B | 2012/08/19 10:02 AM |
Compiler vs. assembly aliasing knowledge? | anon | 2012/08/19 05:07 PM |
Compiler vs. assembly aliasing knowledge? | Ricardo B | 2012/08/19 06:26 PM |
Compiler vs. assembly aliasing knowledge? | anon | 2012/08/19 09:03 PM |
Compiler vs. assembly aliasing knowledge? | anon | 2012/08/20 12:59 AM |
Number of GPRs | David Kanter | 2012/08/17 11:46 AM |
RAT issues as part of reason 1 | Paul A. Clayton | 2012/08/17 01:18 PM |
Number of GPRs | name99 | 2012/11/17 05:37 PM |
Large ARFs increase renaming cost | Paul A. Clayton | 2012/11/17 08:23 PM |
Number of GPRs | David Kanter | 2012/08/16 02:31 PM |
Number of GPRs | Richard Cownie | 2012/08/16 04:17 PM |
32 GPRs ~2-3% | Paul A. Clayton | 2012/08/16 05:27 PM |
Oops, Message-ID: aaed6e38-c7bd-467e-ba41-f40cf1020e5e@googlegroups.com (NT) | Paul A. Clayton | 2012/08/16 05:29 PM |
32 GPRs ~2-3% | Exophase | 2012/08/16 09:06 PM |
R31 as SP/zero is kind of neat (NT) | Paul A. Clayton | 2012/08/17 05:23 AM |
32 GPRs ~2-3% | rwessel | 2012/08/17 07:24 AM |
32 GPRs ~2-3% | Exophase | 2012/08/17 08:16 AM |
32 GPRs ~2-3% | Max | 2012/08/17 03:19 PM |
32 GPRs ~2-3% | name99 | 2012/11/17 06:43 PM |
Number of GPRs | mpx | 2012/08/17 12:11 AM |
Latency and power | Paul A. Clayton | 2012/08/17 05:54 AM |
Number of GPRs | bakaneko | 2012/08/17 02:09 AM |
New Article: ARM Goes 64-bit | Steve | 2012/08/17 01:12 PM |
New Article: ARM Goes 64-bit | David Kanter | 2012/08/19 11:42 AM |
New Article: ARM Goes 64-bit | Doug S | 2012/08/19 01:02 PM |
New Article: ARM Goes 64-bit | Anon | 2012/08/19 06:16 PM |
New Article: ARM Goes 64-bit | Steve | 2012/08/30 06:51 AM |
Scalar vs Vector registers | Robert David Graham | 2012/08/19 04:19 PM |
Scalar vs Vector registers | David Kanter | 2012/08/19 04:29 PM |
New Article: ARM Goes 64-bit | Baserock ARM servers | 2012/08/21 03:13 PM |
Baserock ARM servers | Sysanon | 2012/08/21 03:14 PM |
A-15 virtualization and LPAE? | Paul A. Clayton | 2012/08/21 05:13 PM |
A-15 virtualization and LPAE? | Anon | 2012/08/21 06:13 PM |
Half-depth advantages? | Paul A. Clayton | 2012/08/21 07:42 PM |
Half-depth advantages? | Anon | 2012/08/22 02:33 PM |
Thanks for the information (NT) | Paul A. Clayton | 2012/08/22 03:04 PM |
A-15 virtualization and LPAE? | C. Ladisch | 2012/08/23 10:12 AM |
A-15 virtualization and LPAE? | Paul | 2012/08/23 02:17 PM |
Excessive pessimism | Paul A. Clayton | 2012/08/23 03:08 PM |
Excessive pessimism | David Kanter | 2012/08/23 04:05 PM |
New Article: ARM Goes 64-bit | Michael S | 2012/08/22 06:12 AM |
BTW, Baserock==product, Codethink==company (NT) | Paul A. Clayton | 2012/08/22 07:56 AM |
New Article: ARM Goes 64-bit | Reinoud Zandijk | 2012/08/21 10:27 PM |