Number of GPRs

Article: ARM Goes 64-bit
By: Kenneth Jonsson (kj.delete@this.localhost.org), August 17, 2012 11:54 am
Room: Moderated Discussions
Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on August 17, 2012 6:31 am wrote:

>
> These results are
> wrong - it is trivial to write a function which uses all registers, so pretty
> much impossible they are unused in ~70k instructions. Did you compile with all
> optimizations disabled or perhaps used an old disassembler? (sl,fp,ip were used
> for r10-r12 in the past). Btw you need to include SP and LR as both are GPRs
> (with some special purpose instructions).
>
> Wilco

I compiled with -O2 (recompiled now and double-checked that -O2 and no -O0 was passed to the compiler) and I excluded r13 (stack pointer, which "objdump" show as "sp"), r14 (link register, shown as "lr") and r15 (program counter, listed as "pc"). The compiler is gcc 4.3.3, so not the latest and greatest. I got all this information via objdump, sed, sort and uniq and I'm not a expert on sed. But I opened the full output from "objdump -d" in emacs to double-check that those registers weren't use, only thing I saw with "r11" in was "cr11".

Also, I think my sed reg-exp is correct as they managed to extract the PPC registers r10-r31.

What I did was dumping the whole image file as assembler code, cut out all characters up to the opcode, located every match for r[0-9]+, put the match on a separate line and deleted everything else, i.e.

101e8: e0000492 mul r0, r2, r4

would become

r0
r2
r4

after my "sed" step

Sorted that output, sent it to "uniq -c". I'm not saying that this method is fool-proof or even 100% correct, but it seems to be close enough to get the general trend. And that seem to be that there are very few occasions where 16 or even 8 GPRs seem to be a limiting factor for a modern compiler.

But you are right, it is very odd that three registers would not be used at all, especially as PPC and MIPS used all registers even if quite a lot of them was used quite rarely.

BTW, I tried the same thing on x86_64 using ICC and GCC on a slightly bigger image that contain all the things the ARM version contained + some more stuff. I just post the RAW figures, first column is the number of times the register was used, second column the name (as presented by objdump)

ICC seem to have more spread of its use of registers, but both compilers hardly uses r10 and r11. ICC does generate more instructions tough...

ICC, 550k instructions using at least one of the registers below

20 %xmm11
30 %xmm9
33 %xmm8
47 %r11w
49 %r15w
51 %r11b
55 %r13w
61 %r10w
62 %r9w
64 %r14w
65 %ebp
71 %di
77 %r10b
83 %r12w
83 %r9b
85 %xmm6
88 %xmm10
89 %xmm7
90 %xmm5
91 %r14b
114 %r13b
116 %bx
118 %xmm4
121 %r8w
123 %si
132 %r12b
137 %xmm3
168 %esp
172 %sil
235 %cx
235 %r8b
246 %cs
317 %xmm2
370 %ch
409 %xmm1
431 %dh
536 %bl
676 %dx
688 %bh
749 %xmm0
793 %dil
820 %r15b
849 %ah
1325 %dl
1557 %r11d
1759 %r11
1849 %r10d
2497 %r10
2763 %r9
3159 %r9d
3298 %ax
3900 %r15d
4082 %r14d
4543 %r8
4648 %r13d
4735 %r8d
5724 %r12d
8567 %ebx
10045 %cl
10398 %rip
11137 %edi
13496 %ecx
13505 %esi
14344 %r15
16712 %r14
20295 %r13
20479 %rcx
20579 %edx
21177 %rsp
21901 %rdx
23871 %r12
29124 %rsi
35488 %rbx
36093 %rdi
55063 %al
60391 %eax
69022 %rbp
102955 %rax


GCC, 470k instructions using at least one of the registers below

2 %bpl
2 %xmm15
3 %spl
4 %r11w
6 %xmm12
9 %r10w
10 %r9w
20 %r11b
20 %xmm11
23 %r15w
30 %xmm9
35 %xmm8
37 %r10b
41 %r9b
46 %di
46 %r8w
48 %r13w
57 %r14w
58 %r12w
71 %bx
86 %xmm6
88 %xmm10
89 %xmm7
90 %xmm5
94 %r14b
108 %si
118 %xmm4
131 %cx
131 %ebp
133 %r13b
137 %xmm3
141 %sil
152 %r12b
170 %r8b
317 %xmm2
370 %esp
409 %xmm1
606 %dh
728 %ch
752 %r10d
753 %xmm0
800 %r11d
808 %bl
817 %dx
1002 %r15b
1129 %r10
1134 %cl
1229 %dil
1507 %ah
1598 %r15d
1653 %dl
1768 %r9
1768 %r9d
1962 %r11
1999 %bh
2219 %es
2452 %r14d
2794 %r8
3015 %r8d
3253 %r13d
4517 %r12d
4625 %ax
6272 %r15
7636 %ebx
7732 %ecx
8804 %r14
8896 %edi
9267 %rip
10833 %esi
13820 %r13
14573 %rcx
16122 %edx
17633 %rsp
19526 %rdx
20600 %r12
22977 %rsi
30565 %rdi
34351 %rbx
42926 %rbp
46055 %al
50594 %eax
101687 %rax
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TopicPosted ByDate
New Article: ARM Goes 64-bitDavid Kanter2012/08/14 12:04 AM
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                    Predicated ld/store are usefulanon2012/08/14 07:07 AM
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    Number of GPRsExophase2012/08/16 02:52 PM
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        Ooops, missing link...Kenneth Jonsson2012/08/17 02:44 AM
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                  Pointer compression is atypicalHoward Chu2012/08/22 10:08 PM
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                    Pointer compression is atypicalRichard Cownie2012/08/23 08:44 AM
                      Pointer compression is atypicalHoward Chu2012/08/23 05:17 PM
                        Pointer compression is atypicalanon2012/08/23 08:15 PM
                          Pointer compression is atypicalHoward Chu2012/08/23 09:33 PM
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        Number of GPRsWilco2012/08/17 06:31 AM
          Number of GPRsKenneth Jonsson2012/08/17 11:54 AM
            Number of GPRsExophase2012/08/17 12:44 PM
              Number of GPRsKenneth Jonsson2012/08/17 01:22 PM
                Number of GPRsWilco2012/08/17 02:53 PM
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          Compiler vs. assembly aliasing knowledge?Paul A. Clayton2012/08/17 10:20 AM
            Compiler vs. assembly aliasing knowledge?Exophase2012/08/17 11:09 AM
            Compiler vs. assembly aliasing knowledge?anon2012/08/18 02:23 AM
              Compiler vs. assembly aliasing knowledge?Ricardo B2012/08/19 11:02 AM
                Compiler vs. assembly aliasing knowledge?anon2012/08/19 06:07 PM
                  Compiler vs. assembly aliasing knowledge?Ricardo B2012/08/19 07:26 PM
                    Compiler vs. assembly aliasing knowledge?anon2012/08/19 10:03 PM
                      Compiler vs. assembly aliasing knowledge?anon2012/08/20 01:59 AM
        Number of GPRsDavid Kanter2012/08/17 12:46 PM
          RAT issues as part of reason 1Paul A. Clayton2012/08/17 02:18 PM
        Number of GPRsname992012/11/17 06:37 PM
          Large ARFs increase renaming costPaul A. Clayton2012/11/17 09:23 PM
    Number of GPRsDavid Kanter2012/08/16 03:31 PM
    Number of GPRsRichard Cownie2012/08/16 05:17 PM
    32 GPRs ~2-3%Paul A. Clayton2012/08/16 06:27 PM
      Oops, Message-ID: aaed6e38-c7bd-467e-ba41-f40cf1020e5e@googlegroups.com (NT)Paul A. Clayton2012/08/16 06:29 PM
      32 GPRs ~2-3%Exophase2012/08/16 10:06 PM
        R31 as SP/zero is kind of neat (NT)Paul A. Clayton2012/08/17 06:23 AM
        32 GPRs ~2-3%rwessel2012/08/17 08:24 AM
          32 GPRs ~2-3%Exophase2012/08/17 09:16 AM
            32 GPRs ~2-3%Max2012/08/17 04:19 PM
      32 GPRs ~2-3%name992012/11/17 07:43 PM
    Number of GPRsmpx2012/08/17 01:11 AM
      Latency and powerPaul A. Clayton2012/08/17 06:54 AM
    Number of GPRsbakaneko2012/08/17 03:09 AM
  New Article: ARM Goes 64-bitSteve2012/08/17 02:12 PM
    New Article: ARM Goes 64-bitDavid Kanter2012/08/19 12:42 PM
      New Article: ARM Goes 64-bitDoug S2012/08/19 02:02 PM
      New Article: ARM Goes 64-bitAnon2012/08/19 07:16 PM
      New Article: ARM Goes 64-bitSteve2012/08/30 07:51 AM
  Scalar vs Vector registersRobert David Graham2012/08/19 05:19 PM
    Scalar vs Vector registersDavid Kanter2012/08/19 05:29 PM
  New Article: ARM Goes 64-bitBaserock ARM servers2012/08/21 04:13 PM
    Baserock ARM serversSysanon2012/08/21 04:14 PM
    A-15 virtualization and LPAE?Paul A. Clayton2012/08/21 06:13 PM
      A-15 virtualization and LPAE?Anon2012/08/21 07:13 PM
        Half-depth advantages?Paul A. Clayton2012/08/21 08:42 PM
          Half-depth advantages?Anon2012/08/22 03:33 PM
            Thanks for the information (NT)Paul A. Clayton2012/08/22 04:04 PM
      A-15 virtualization and LPAE?C. Ladisch2012/08/23 11:12 AM
        A-15 virtualization and LPAE?Paul2012/08/23 03:17 PM
        Excessive pessimismPaul A. Clayton2012/08/23 04:08 PM
          Excessive pessimismDavid Kanter2012/08/23 05:05 PM
    New Article: ARM Goes 64-bitMichael S2012/08/22 07:12 AM
      BTW, Baserock==product, Codethink==company (NT)Paul A. Clayton2012/08/22 08:56 AM
  New Article: ARM Goes 64-bitReinoud Zandijk2012/08/21 11:27 PM
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