Number of GPRs

Article: ARM Goes 64-bit
By: David Kanter (dkanter.delete@this.realworldtech.com), August 17, 2012 12:46 pm
Room: Moderated Discussions
> So to spin the question a bit: what are the
> downsides of a large number of GPRs? It has to be fairly big trade-offs to be
> made somewhere as very few architectures seem to move beyond 32 GPRs and AMD did
> for some reason settle at 16 GPRs when they designed x86_64. Not a perfect
> comparison, but the performance difference between IA32 and x86_64 is very small
> so IA32 cannot be held back too much by its lack of GPRs.
>
> One point of
> reference to compare IA32 vs x86_64 is . Looking at the single core results for
> C and Java show that some things are faster and some things are slower on IA32,
> but the results are with very few exceptions VERY similar.
>
> Sorry for a long
> post, interesting topic i.m.h.o :)

Very good question. There are a number of downsides:

1. Out-of-order execution

With OOOE you need to rename all your architectural registers. That means your physical register file for ARM needs to include 32 GPRs, 32 VPRs just to hold architectural data. For each additional instruction you want in the re-order window, you need a register to hold the result.

So say you want a window of 64 instructions, that means 64 extra integer registers. But you also need extra VPRs so you don't get limited on FP code (worst case, 64 VPRs). So you might need a physical register file that has around 96 GPRs and 96 VPRs. That's pretty darn big.

And remember, your renaming structures tend to need multiple ports and are pretty big and power hungry.

2. Multi-threading

To do multi-threading, you have to duplicate the architectural state. So each thread requires an extra 32+32 registers, twice what would be necessary with 16 registers. Doing a heavily threaded CPU (4-8 threads) is obviously a lot easier with smaller register files.

3. Context switching, interrupts, exceptions

You have to push/pop to/from memory. This isn't a super big deal though.

4. Larger instructions

32 registers --> 5 bit field, instead of 4-bit. Most instructions are 3-operand, so you're talking about saving 3-bits/instruction. We already saw that ARM had to decrease the branch displacement, precisely because of the larger register fields.

Can anyone add other drawbacks?

David
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New Article: ARM Goes 64-bitDavid Kanter2012/08/14 12:04 AM
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        MONITOR/MWAITanonymou52012/08/14 11:07 AM
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                  Predicated ld/store are usefulnone2012/08/14 06:56 AM
                    Predicated ld/store are usefulanon2012/08/14 07:07 AM
                    Predicated stores might not be that badPaul A. Clayton2012/08/14 07:27 AM
                      Predicated stores might not be that badDavid Kanter2012/08/15 01:14 AM
                        Predicated stores might not be that badMichael S2012/08/15 11:41 AM
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          OT: Conrad's "Youth"Richard Cownie2012/08/14 07:20 AM
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                                      Amazing!EduardoS2012/11/28 07:25 PM
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  Minor suggested correctionPaul A. Clayton2012/08/14 08:33 AM
    Minor suggested correctionanon2012/08/14 08:57 AM
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    Number of GPRsExophase2012/08/16 02:52 PM
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              Brute force seems to workbakaneko2012/08/17 11:15 AM
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            Pointer compression is atypicalPaul A. Clayton2012/08/17 10:43 AM
              Pointer compression is atypicalRichard Cownie2012/08/17 12:57 PM
                Pointer compression is atypicalHoward Chu2012/08/22 10:17 PM
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                Pointer compression is atypicalRichard Cownie2012/08/17 04:13 PM
                  Pointer compression is atypicalRicardo B2012/08/19 10:44 AM
                  Pointer compression is atypicalHoward Chu2012/08/22 10:08 PM
                    Unified libraries?Paul A. Clayton2012/08/23 07:49 AM
                    Pointer compression is atypicalRichard Cownie2012/08/23 08:44 AM
                      Pointer compression is atypicalHoward Chu2012/08/23 05:17 PM
                        Pointer compression is atypicalanon2012/08/23 08:15 PM
                          Pointer compression is atypicalHoward Chu2012/08/23 09:33 PM
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        Number of GPRsWilco2012/08/17 06:31 AM
          Number of GPRsKenneth Jonsson2012/08/17 11:54 AM
            Number of GPRsExophase2012/08/17 12:44 PM
              Number of GPRsKenneth Jonsson2012/08/17 01:22 PM
                Number of GPRsWilco2012/08/17 02:53 PM
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            Compiler vs. assembly aliasing knowledge?Exophase2012/08/17 11:09 AM
            Compiler vs. assembly aliasing knowledge?anon2012/08/18 02:23 AM
              Compiler vs. assembly aliasing knowledge?Ricardo B2012/08/19 11:02 AM
                Compiler vs. assembly aliasing knowledge?anon2012/08/19 06:07 PM
                  Compiler vs. assembly aliasing knowledge?Ricardo B2012/08/19 07:26 PM
                    Compiler vs. assembly aliasing knowledge?anon2012/08/19 10:03 PM
                      Compiler vs. assembly aliasing knowledge?anon2012/08/20 01:59 AM
        Number of GPRsDavid Kanter2012/08/17 12:46 PM
          RAT issues as part of reason 1Paul A. Clayton2012/08/17 02:18 PM
        Number of GPRsname992012/11/17 06:37 PM
          Large ARFs increase renaming costPaul A. Clayton2012/11/17 09:23 PM
    Number of GPRsDavid Kanter2012/08/16 03:31 PM
    Number of GPRsRichard Cownie2012/08/16 05:17 PM
    32 GPRs ~2-3%Paul A. Clayton2012/08/16 06:27 PM
      Oops, Message-ID: aaed6e38-c7bd-467e-ba41-f40cf1020e5e@googlegroups.com (NT)Paul A. Clayton2012/08/16 06:29 PM
      32 GPRs ~2-3%Exophase2012/08/16 10:06 PM
        R31 as SP/zero is kind of neat (NT)Paul A. Clayton2012/08/17 06:23 AM
        32 GPRs ~2-3%rwessel2012/08/17 08:24 AM
          32 GPRs ~2-3%Exophase2012/08/17 09:16 AM
            32 GPRs ~2-3%Max2012/08/17 04:19 PM
      32 GPRs ~2-3%name992012/11/17 07:43 PM
    Number of GPRsmpx2012/08/17 01:11 AM
      Latency and powerPaul A. Clayton2012/08/17 06:54 AM
    Number of GPRsbakaneko2012/08/17 03:09 AM
  New Article: ARM Goes 64-bitSteve2012/08/17 02:12 PM
    New Article: ARM Goes 64-bitDavid Kanter2012/08/19 12:42 PM
      New Article: ARM Goes 64-bitDoug S2012/08/19 02:02 PM
      New Article: ARM Goes 64-bitAnon2012/08/19 07:16 PM
      New Article: ARM Goes 64-bitSteve2012/08/30 07:51 AM
  Scalar vs Vector registersRobert David Graham2012/08/19 05:19 PM
    Scalar vs Vector registersDavid Kanter2012/08/19 05:29 PM
  New Article: ARM Goes 64-bitBaserock ARM servers2012/08/21 04:13 PM
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      A-15 virtualization and LPAE?Anon2012/08/21 07:13 PM
        Half-depth advantages?Paul A. Clayton2012/08/21 08:42 PM
          Half-depth advantages?Anon2012/08/22 03:33 PM
            Thanks for the information (NT)Paul A. Clayton2012/08/22 04:04 PM
      A-15 virtualization and LPAE?C. Ladisch2012/08/23 11:12 AM
        A-15 virtualization and LPAE?Paul2012/08/23 03:17 PM
        Excessive pessimismPaul A. Clayton2012/08/23 04:08 PM
          Excessive pessimismDavid Kanter2012/08/23 05:05 PM
    New Article: ARM Goes 64-bitMichael S2012/08/22 07:12 AM
      BTW, Baserock==product, Codethink==company (NT)Paul A. Clayton2012/08/22 08:56 AM
  New Article: ARM Goes 64-bitReinoud Zandijk2012/08/21 11:27 PM
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