RAT issues as part of reason 1

Article: ARM Goes 64-bit
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), August 17, 2012 2:18 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on August 17, 2012 12:46 pm wrote:
[snip]
> Can anyone add other drawbacks?

In the subthread starting here, issues involving the RAT were mentioned (a part of your reason 1). A larger architected register set also increases the overhead of making checkpoints for speculation recovery (if any are provided besides the retirement checkpoint) and restoring from checkpoints.

RAT and register file issues can be reduced by having an asymmetric register file. E.g., an ISA could provide an L2 register file which is only readable for one source operand in each instruction. Banking hints and guarantees might be useful (even in the register file of an OoO design). Preferential use of specific registers could also allow some optimizations (e.g., recent x86 optimizations with respect to the stack pointer). (An L2 register file might be handled something like a store queue and cache rather than with a complete RAT; if updates are infrequent, the extra energy to write values into the main L2 RF at commit might be less than the cost of memory operations that would replace L2 accesses.)

Providing the ability to zero registers would allow early register release (other small values might likewise be "inlined" into the 'physical' register name), reducing the overhead when registers are not actually being used (or are being used only for small values). (There are a lot of papers on dealing with register file size, power, and latency issues, especially for wide OoO designs.) I seem to recall that AVX provides special zeroing instructions; such could be used to free physical registers early and keep them free (using a special is_zero name in the RAT or a is_zero bit).

In theory, an ISA could moderate the multithreading penalty by supporting smaller contexts. Registers could be allocated to threads in groups of (e.g.) 8 registers with unallocated registers being treated as zero registers (or perhaps as shared registers [possibly with only the owner thread being allowed to write into such shared registers or with only privileged code being able to perform such writes]). (One could even imagine the use of such register blocks as something like register windows.)
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New Article: ARM Goes 64-bitDavid Kanter2012/08/14 12:04 AM
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          RAT issues as part of reason 1Paul A. Clayton2012/08/17 02:18 PM
        Number of GPRsname992012/11/17 06:37 PM
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      Oops, Message-ID: aaed6e38-c7bd-467e-ba41-f40cf1020e5e@googlegroups.com (NT)Paul A. Clayton2012/08/16 06:29 PM
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          32 GPRs ~2-3%Exophase2012/08/17 09:16 AM
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          Excessive pessimismDavid Kanter2012/08/23 05:05 PM
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      BTW, Baserock==product, Codethink==company (NT)Paul A. Clayton2012/08/22 08:56 AM
  New Article: ARM Goes 64-bitReinoud Zandijk2012/08/21 11:27 PM
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